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31. 发明申请

US20090230987A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20090230987A1
公开(公告)日：2009-09-17
申请号：US12379773
申请日：2009-02-27
申请人： Jun Ikeda , Morihisa Hirata
发明人： Jun Ikeda , Morihisa Hirata
IPC分类号： G01R31/26
CPC分类号： G01R31/318511 , G01R31/31722 , G11C29/006 , G11C29/20 , G11C2029/1206 , G11C2029/3602 , G11C2029/4402
摘要： An exemplary aspect of an embodiment of the present invention is a semiconductor device including a plurality of test elements formed in an array on a semiconductor substrate, an address signal generating portion that generates an address signal corresponding to each of the test elements, and a digital-to-analog converter that converts the address signal into an analog signal and outputs the converted analog signal. The present invention enables to recognize which DUT is being measured.
摘要翻译：本发明的一个实施例的示例性方面是一种半导体器件，包括在半导体衬底上形成为阵列的多个测试元件，产生与每个测试元件对应的地址信号的地址信号产生部分，以及数字模拟转换器，其将地址信号转换为模拟信号并输出转换的模拟信号。本发明能够识别正在测量哪个DUT。

32. 发明申请

US20080283986A1 System-in-package type semiconductor device 审中-公开
标题翻译：系统级封装型半导体器件
公开(公告)号：US20080283986A1
公开(公告)日：2008-11-20
申请号：US11977463
申请日：2007-10-25
申请人： Morihisa Hirata
发明人： Morihisa Hirata
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L27/0251 , H01L23/50 , H01L23/5286 , H01L23/60 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0292 , H01L2224/0554 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/731 , H01L2224/73207 , H01L2224/73265 , H01L2924/00014 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second semiconductor chip 1120 to which electric power is supplied from second power supply wiring 1124, and second ground wiring 1125 coupled to the second circuit unit. The first semiconductor chip includes a first interface circuit unit 1412, and the second circuit unit includes a second interface circuit unit 1121 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring 1414 is coupled to the second ground wiring 1424 through a protection circuit 1442, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.
摘要翻译：一种系统级封装型半导体器件，包括多个半导体芯片，从第一电源布线1111供给电力的第一半导体芯片1110和与第一电路单元耦合的第一接地布线1112。此外，系统级封装型半导体器件包括从第二电源布线1124供给电力的第二半导体芯片1120和耦合到第二电路单元的第二接地布线1125。第一半导体芯片包括第一接口电路单元1412，第二电路单元包括被配置为向第一接口电路单元输入或输出信号的第二接口电路单元1121。第一接地线1414通过保护电路1442耦合到第二接地线1424，并且第二接口电路单元被放置在第一接口电路单元附近。

33. 发明授权

US07196377B2 MOS type semiconductor device having electrostatic discharge protection arrangement 失效
标题翻译：具有静电放电保护装置的MOS型半导体器件
公开(公告)号：US07196377B2
公开(公告)日：2007-03-27
申请号：US11111797
申请日：2005-04-22
申请人： Noriyuki Kodama , Koichi Sawahata , Morihisa Hirata
发明人： Noriyuki Kodama , Koichi Sawahata , Morihisa Hirata
IPC分类号： H01L23/62 , H01L29/72 , H01L29/73 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0277 , H01L23/60 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.
摘要翻译：在具有静电放电保护装置的半导体器件中，半导体衬底呈现出第一导电类型。在半导体衬底中形成各自呈现第二导电类型的第一和第二杂质区。在第一和第二杂质区之间的半导体衬底中形成沟道区。第一导电区域限定在沟道区附近的第一杂质区上。在第一杂质区域上限定第二导电区域，以供给静电放电电流。在第一杂质区域上限定第三导电区域，以在第一和第二导电区域之间建立电连接。在第三导电区域中限定至少一个热辐射区域，以便至少部分与第一导电区域隔离并与第一导电区域热接触。

34. 发明授权

US06629295B1 Design automation method and device 失效
标题翻译：设计自动化方法和设备
公开(公告)号：US06629295B1
公开(公告)日：2003-09-30
申请号：US09339117
申请日：1999-06-24
申请人： Tetsuya Akimoto , Morihisa Hirata
发明人： Tetsuya Akimoto , Morihisa Hirata
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5036
摘要： A design automation method is provided which reduces complication of design work resulting from individual verification of a plurality of objects to be verified, for example, electromigration and hot carrier effect. Limiting values are prepared individually for the objects to be verified while a combined limiting value is obtained by combining these limiting values. By the use of the combined limiting value, verification of reliability is performed for all the objects. Specifically, when applied to the electromigration and the hot carrier effect as the objects to be verified, verification can simultaneously be performed upon frequency limiting values for the electromigration and the hot carrier effect.
摘要翻译：提供了一种设计自动化方法，其减少了由待验证的多个对象的个体验证产生的设计工作的复杂性，例如电迁移和热载体效应。通过组合这些限制值来获得对待验证对象单独准备限制值，同时获得组合的限制值。通过使用组合的限制值，对所有对象执行可靠性验证。具体来说，当作为要验证的对象应用于电迁移和热载体效应时，可以在电迁移和热载流子效应的频率限制值的同时进行验证。

35. 发明授权

US06600210B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06600210B1
公开(公告)日：2003-07-29
申请号：US09679583
申请日：2000-10-04
申请人： Osamu Kato , Morihisa Hirata , Yasuyuki Morishita
发明人： Osamu Kato , Morihisa Hirata , Yasuyuki Morishita
IPC分类号： H01L2900
CPC分类号： H01L27/0288 , H01L27/0266
摘要： A semiconductor device is provided, which is provided with a high resistance to surge currents. The semiconductor device comprises three N+ diffusion layers 4a, 4b, and 4c in a region surrounded by an element-separating insulating film 3a. The N+ diffusion layer 4a forms a source diffusion layer of an N-channel MOS transistor 11a, the N+ diffusion layer 4c forms a source diffusion layer of another N-channel MOS transistor 11b, and the N+ diffusion layer 4b forms drain diffusion layers for two N-channel MOS transistors 11a and 11b. That is, respective drain diffusion layers of two N-channel MOS transistors are shared. Furthermore, a ring-shaped mask insulating film 18 is formed on the N+ diffusion layer 4b. A silicide layer 6b is formed on the N+ diffusion layer 4b except the area covered by the ring-shaped mask insulating film 18.
摘要翻译：提供了一种半导体器件，其具有高的浪涌电流电阻。半导体器件在由元件分离绝缘膜3a包围的区域中包括三个N +扩散层4a，4b和4c。 N +扩散层4a形成N沟道MOS晶体管11a的源极扩散层，N +扩散层4c形成另一N沟道MOS晶体管11b的源极扩散层，N +扩散层4b形成漏极扩散层2 N沟道MOS晶体管11a和11b。也就是说，两个N沟道MOS晶体管的各个漏极扩散层被共享。此外，在N +扩散层4b上形成环状掩模绝缘膜18。除了由环形掩模绝缘膜18覆盖的区域之外，在N +扩散层4b上形成硅化物层6b。

36. 发明授权

US5905287A Semiconductor device with high voltage protection 失效
标题翻译：具有高电压保护的半导体器件
公开(公告)号：US5905287A
公开(公告)日：1999-05-18
申请号：US837344
申请日：1997-04-17
申请人： Morihisa Hirata
发明人： Morihisa Hirata
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/78 , H02H9/04 , H01L23/62
CPC分类号： H01L27/0266 , H01L2924/0002 , H02H9/046
摘要： The object of the present invention is to provide a semiconductor device, which has a high protective capability against an excessive voltage applied from the outside. The device is provided, in its analog switch 30, with a P type dummy transistor 11 whose drain terminal is connected to a P type diffusion layer in the outside of a P type transfer gate 4 and whose gate and source terminals are connected to a power supply potential, and an N type dummy transistor 12 whose drain terminal is connected to an N type diffusion layer in the outside of an N type transfer gate 5 and whose gate and source terminals are connected to a ground potential, and when an excessive voltage is applied from the outside, an excessive current is made to flow through the P type and N type dummy transistors 11 and 12 to the power supply potential or the ground potential.
摘要翻译：本发明的目的是提供一种对从外部施加的过大电压具有高保护能力的半导体器件。该器件在其模拟开关30中设置有P型虚设晶体管11，其漏极端子连接到P型传输门4的外部的P型扩散层，其栅极和源极端子连接到功率 N型虚设晶体管12，其漏极端子连接到N型转移栅极5的外部的N型扩散层，栅极和源极端子接地电位，并且当过电压为从外部施加过多的电流使P型和N型虚拟晶体管11,12流过电源电位或地电位。

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