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1. 发明授权

US08270132B2 Semiconductor device with a plurality of power supply systems 有权
标题翻译：具有多个电源系统的半导体装置
公开(公告)号：US08270132B2
公开(公告)日：2012-09-18
申请号：US12929206
申请日：2011-01-07
申请人： Masanori Tanaka , Morihisa Hirata , Hitoshi Okamoto
发明人： Masanori Tanaka , Morihisa Hirata , Hitoshi Okamoto
IPC分类号： H02H9/04
CPC分类号： H03K19/00315 , H01L27/0251 , H01L27/0292
摘要： A protection circuit that includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, the second power supply system being connected to the first power supply system via a signal line through which signal transfer is performed between a circuit in the first power supply system and a circuit in the second power supply system, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system controls a switch, the switch being provided between the signal line and the first power supply.
摘要翻译：一种保护电路，其包括包括第一电源和第一接地的第一电源系统，包括第二电源和第二接地的第二电源系统，所述第二电源系统经由在第一电源系统中的电路和第二电源系统中的电路之间执行信号传输的信号线，以及当耦合到施加到第一电源系统的静电放电（ESD）应力时的控制电路，电源系统控制开关，开关设在信号线和第一电源之间。

2. 发明授权

US08008727B2 Semiconductor integrated circuit device including a pad and first mosfet 有权
标题翻译：半导体集成电路器件包括焊盘和第一mosfet
公开(公告)号：US08008727B2
公开(公告)日：2011-08-30
申请号：US12010991
申请日：2008-01-31
申请人： Hitoshi Okamoto , Morihisa Hirata
发明人： Hitoshi Okamoto , Morihisa Hirata
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and a potential control circuit 10 that controls a potential Vb of the gate terminal and the backgate of the n-type MOSFET M1a based on a potential Vin of the pad PAD. The potential control circuit 10 comprises n-type MOSFETs M2 and M3; the n-type MOSFET M1a has its gate terminal and backgate connected to backgates and drains of the n-type MOSFETs M2 and M3; the n-type MOSFET M2 has its source grounded and its gate terminal connected to the pad PAD via a resistance R; and the n-type MOSFET M3 has its source connected to the pad PAD and its gate terminal grounded.
摘要翻译：以减少连接在焊盘和地之间的MOSFET中的漏电流。提供用于输入或输出信号的焊盘PAD，连接在焊盘PAD和地之间并且其栅极端子和背板共同连接的n型MOSFET M1a和控制电位Vb的电位Vb的电位控制电路10 基于焊盘PAD的电位Vin的n型MOSFET M1a的栅极端子和背栅极。电位控制电路10包括n型MOSFET M2和M3; n型MOSFET M1a的栅极端子和背栅极连接到n型MOSFET M2和M3的后栅和漏极; n型MOSFET M2的源极接地，其栅极端子通过电阻R连接到焊盘PAD; 并且n型MOSFET M3的源极连接到焊盘PAD并且其栅极端子接地。

3. 发明授权

US07552404B2 Semiconductor integrated device and apparatus for designing the same 有权
公开(公告)号：US07552404B2
公开(公告)日：2009-06-23
申请号：US11444617
申请日：2006-06-01
申请人： Morihisa Hirata
发明人： Morihisa Hirata
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78 , H01L23/5286 , H01L23/60 , H01L27/0251 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.

4. 发明授权

US07312517B2 System-in-package type semiconductor device 有权
标题翻译：系统级封装型半导体器件
公开(公告)号：US07312517B2
公开(公告)日：2007-12-25
申请号：US11244877
申请日：2005-10-06
申请人： Morihisa Hirata
发明人： Morihisa Hirata
IPC分类号： H01L23/02 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/0251 , H01L23/50 , H01L23/5286 , H01L23/60 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0292 , H01L2224/0554 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/731 , H01L2224/73207 , H01L2224/73265 , H01L2924/00014 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second semiconductor chip 1120 to which electric power is supplied from second power supply wiring 1124, and second ground wiring 1125 coupled to the second circuit unit. The first semiconductor chip includes a first interface circuit unit 1412, and the second circuit unit includes a second interface circuit unit 1121 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring 1414 is coupled to the second ground wiring 1424 through a protection circuit 1442, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.
摘要翻译：一种系统级封装型半导体器件，包括多个半导体芯片，从第一电源布线1111供给电力的第一半导体芯片1110和与第一电路单元耦合的第一接地布线1112。此外，系统级封装型半导体器件包括从第二电源布线1124供给电力的第二半导体芯片1120和耦合到第二电路单元的第二接地布线1125。第一半导体芯片包括第一接口电路单元1412，第二电路单元包括被配置为向第一接口电路单元输入或输出信号的第二接口电路单元1121。第一接地线1414通过保护电路1442耦合到第二接地线1424，并且第二接口电路单元被放置在第一接口电路单元附近。

5. 发明申请

US20060103421A1 System-in-package type semiconductor device 有权
标题翻译：系统级封装型半导体器件
公开(公告)号：US20060103421A1
公开(公告)日：2006-05-18
申请号：US11244877
申请日：2005-10-06
申请人： Morihisa Hirata
发明人： Morihisa Hirata
IPC分类号： H01L23/34 , H03K19/0175
CPC分类号： H01L27/0251 , H01L23/50 , H01L23/5286 , H01L23/60 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L27/0292 , H01L2224/0554 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/731 , H01L2224/73207 , H01L2224/73265 , H01L2924/00014 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 1110 to which electric power is supplied from first power supply wiring 1111, and first ground wiring 1112 to which the first circuit unit is coupled. Moreover, the system-in-package type semiconductor device includes a second semiconductor chip 1120 to which electric power is supplied from second power supply wiring 1124, and second ground wiring 1125 coupled to the second circuit unit. The first semiconductor chip includes a first interface circuit unit 1412, and the second circuit unit includes a second interface circuit unit 1121 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring 1414 is coupled to the second ground wiring 1424 through a protection circuit 1442, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.
摘要翻译：一种系统级封装型半导体器件，包括多个半导体芯片，从第一电源布线1111供给电力的第一半导体芯片1110和与第一电路单元耦合的第一接地布线1112。此外，系统级封装型半导体器件包括从第二电源布线1124供给电力的第二半导体芯片1120和耦合到第二电路单元的第二接地布线1125。第一半导体芯片包括第一接口电路单元1412，第二电路单元包括被配置为向第一接口电路单元输入或输出信号的第二接口电路单元1121。第一接地线1414通过保护电路1442耦合到第二接地线1424，并且第二接口电路单元被放置在第一接口电路单元附近。

6. 发明授权

US06975979B2 Method and computer software product for calculating and presenting a numerical value representative of a property of a circuit 失效
标题翻译：用于计算和呈现代表电路性质的数值的方法和计算机软件产品
公开(公告)号：US06975979B2
公开(公告)日：2005-12-13
申请号：US09347409
申请日：1999-07-06
申请人： Tetsuya Akimoto , Morihisa Hirata
发明人： Tetsuya Akimoto , Morihisa Hirata
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5022
摘要： To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.
摘要翻译：计算引脚延迟时间，即从输入引脚到逻辑块输出引脚的延迟时间，以及块到块延迟时间，这是从一个块的输出引脚到输入的延迟时间引脚，首先，引脚延迟时间和块到块延迟时间由热载流子效应导致的老化过程计算，其次由连接到输入引脚的老化晶体管引起的降级和输出引脚，最后，引脚延迟时间和块到块延迟时间由劣化率修改。

7. 发明申请

US20050236672A1 MOS type semiconductor device having electrostatic discharge protection arrangement 失效
标题翻译：具有静电放电保护装置的MOS型半导体器件
公开(公告)号：US20050236672A1
公开(公告)日：2005-10-27
申请号：US11111797
申请日：2005-04-22
申请人： Noriyuki Kodama , Koichi Sawahata , Morihisa Hirata
发明人： Noriyuki Kodama , Koichi Sawahata , Morihisa Hirata
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0277 , H01L23/60 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.
摘要翻译：在具有静电放电保护装置的半导体器件中，半导体衬底呈现出第一导电类型。在半导体衬底中形成各自呈现第二导电类型的第一和第二杂质区。在第一和第二杂质区之间的半导体衬底中形成沟道区。第一导电区域限定在沟道区附近的第一杂质区上。在第一杂质区域上限定第二导电区域，以供给静电放电电流。在第一杂质区域上限定第三导电区域，以在第一和第二导电区域之间建立电连接。在第三导电区域中限定至少一个热辐射区域，以便至少部分与第一导电区域隔离并与第一导电区域热接触。

8. 发明授权

US06191454B1 Protective resistance element for a semiconductor device 失效
标题翻译：半导体器件的保护电阻元件
公开(公告)号：US06191454B1
公开(公告)日：2001-02-20
申请号：US08988474
申请日：1997-12-10
申请人： Morihisa Hirata , Kouji Terai , Toshiya Hatta
发明人： Morihisa Hirata , Kouji Terai , Toshiya Hatta
IPC分类号： H01L2362
CPC分类号： H01L27/0251
摘要： A semiconductor device includes a transistor and a protective resistance element. The transistor has first and second impurity regions of a first conductivity type formed on a surface of a substrate and serving as a source and a drain, respectively, and a gate electrode formed on a channel region sandwiched between the first and second impurity regions through a gate insulating film. The protective resistance element has a third impurity region of the first conductivity type formed on the surface of the substrate to be separated from the second impurity region by a predetermined distance, a control electrode formed on the substrate through an insulating film in a surface region sandwiched between the second and third impurity regions, and a well of the first conductivity type formed on the surface of the substrate in the surface region sandwiched between the second and third impurity regions to come into contact with them. The control electrode is connected to the second impurity region, and the well has an impurity concentration lower than those of the second and third impurity regions.
摘要翻译：半导体器件包括晶体管和保护电阻元件。该晶体管分别具有第一和第二第一导电类型的杂质区，该第一和第二杂质区分别形成在衬底的表面上并用作源极和漏极;以及栅电极，其形成在夹在第一和第二杂质区之间的沟道区上，栅极绝缘膜。保护电阻元件具有第一导电类型的第三杂质区域，形成在衬底的表面上以与第二杂质区分离预定距离，控制电极通过绝缘膜在夹在在第二和第三杂质区域之间形成的第一导电类型的阱和在夹在第二和第三杂质区域之间的表面区域中形成在基板表面上以与它们接触的阱。控制电极连接到第二杂质区，阱的杂质浓度低于第二和第三杂质区的杂质浓度。

9. 发明授权

US07624365B2 Semiconductor integrated device and apparatus for designing the same 有权
标题翻译：半导体集成装置及其设计装置
公开(公告)号：US07624365B2
公开(公告)日：2009-11-24
申请号：US12288083
申请日：2008-10-16
申请人： Morihisa Hirata
发明人： Morihisa Hirata
IPC分类号： G06F17/50 , H03K5/08 , H01L23/62 , H02H3/00
CPC分类号： G06F17/505 , G06F2217/78 , H01L23/5286 , H01L23/60 , H01L27/0251 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit to which electric power is supplied from second power supply wiring, and second ground wiring coupled to the second circuit unit. The first circuit unit includes a first interface circuit unit, and the second circuit unit includes a second interface circuit unit configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The second interface circuit unit is placed in the vicinity of the first interface circuit unit according to a determined arrangement.
摘要翻译：半导体集成装置包括多个电力系统电路单元，从第一电源布线供给电力的第一电路单元和与第一电路单元耦合的第一接地布线。此外，半导体集成器件包括从第二电源布线供给电力的第二电路单元和耦合到第二电路单元的第二接地布线。第一电路单元包括第一接口电路单元，第二电路单元包括被配置为向第一接口电路单元输入信号或从第一接口电路单元输出信号的第二接口电路单元。第二接口电路单元根据确定的布置被放置在第一接口电路单元的附近。

10. 发明申请

US20090077517A1 Semiconductor intergrated device and apparatus for designing the same 有权
标题翻译：半导体集成装置及其设计装置
公开(公告)号：US20090077517A1
公开(公告)日：2009-03-19
申请号：US12288084
申请日：2008-10-16
申请人： Morihisa Hirata
发明人： Morihisa Hirata
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78 , H01L23/5286 , H01L23/60 , H01L27/0251 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit 101 to which electric power is supplied from first power supply wiring 106, and first ground wiring 109 to which the first circuit unit is coupled. Moreover, the semiconductor integrated device includes a second circuit unit 102 to which electric power is supplied from second power supply wiring 113, and second ground wiring 116 coupled to the second circuit unit.The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground wiring through a protection circuit 117, and the second interface circuit unit is placed in the vicinity of the first interface circuit unit.
摘要翻译：半导体集成装置包括多个电力系统电路单元，从第一电源布线106供给电力的第一电路单元101和与第一电路单元耦合的第一接地布线109。此外，半导体集成器件包括从第二电源布线113供给电力的第二电路单元102和耦合到第二电路单元的第二接地布线116。第一电路单元包括第一接口电路单元104，第二电路单元包括被配置为向第一接口电路单元输入信号或从第一接口电路单元输出信号的第二接口电路单元111。第一接地线路通过保护电路117耦合到第二接地线路，并且第二接口电路单元被放置在第一接口电路单元附近。

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