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31. 发明申请

US20120005026A1 METHODS, SYSTEMS AND COMPUTER READABLE MEDIA FOR UTILIZING A CONSUMER OPT-IN MANAGEMENT SYSTEM 审中-公开
标题翻译：使用消费者可选管理系统的方法，系统和计算机可读介质
公开(公告)号：US20120005026A1
公开(公告)日：2012-01-05
申请号：US13118046
申请日：2011-05-27
申请人： Mohammad Khan , Pradeep Kumar , Hans Bielefeld Reisgies , Kaushik Roy , Roshan Vijayshankar
发明人： Mohammad Khan , Pradeep Kumar , Hans Bielefeld Reisgies , Kaushik Roy , Roshan Vijayshankar
IPC分类号： G06Q30/00
CPC分类号： G06Q30/02 , G06Q30/0224 , G06Q30/0238 , G06Q30/0267 , H04W4/00
摘要： Methods, systems, and computer readable media for utilizing a consumer opt-in management system are disclosed. According to one aspect, the method includes interfacing a near field communication (NFC) enabled mobile device with a touch point associated with an electronic marketing program to obtain touch point identification information from the touch point and receiving, at a trigger management server (TMS), an opt-in request message from the NFC enabled mobile device, wherein the opt-in request message includes a subscriber identifier associated with the NFC enabled mobile device and the touch point identification information. The method further includes accessing a business rules database using at least one of the subscriber identifier and the touch point identification information from the opt-in request message to identify an electronic marketing program identifier and using the electronic marketing program identifier to trigger the provisioning of content data associated with the electronic marketing program to the NFC enabled mobile device.
摘要翻译：公开了用于利用消费者选择加入管理系统的方法，系统和计算机可读介质。根据一个方面，所述方法包括将支持近场通信（NFC）的移动设备与与电子营销程序相关联的触摸点进行接口，以从触摸点获得触摸点识别信息，并在触发管理服务器（TMS）来自NFC启用的移动设备的选择加入请求消息，其中所述选择加入请求消息包括与启用NFC的移动设备相关联的用户标识符和所述触摸点识别信息。该方法还包括使用来自选择加入请求消息的订户标识符和接触点识别信息中的至少一个来访问业务规则数据库，以识别电子营销程序标识符并使用电子营销程序标识符来触发内容的提供将与电子营销程序相关联的数据传送到支持NFC的移动设备。

32. 发明授权

US07328413B2 Method and circuit for reducing leakage and increasing read stability in a memory device 有权
标题翻译：用于减少泄漏并增加存储器件中的读取稳定性的方法和电路
公开(公告)号：US07328413B2
公开(公告)日：2008-02-05
申请号：US11066402
申请日：2005-02-25
申请人： Hyung-il Kim , Jae-Joon Kim , Kaushik Roy
发明人： Hyung-il Kim , Jae-Joon Kim , Kaushik Roy
IPC分类号： G06F17/50 , G11C5/14
CPC分类号： G11C7/02 , G11C11/412
摘要： A device and method for increasing the read stability of a memory device includes sizing a sleep transistor according to a size ratio of the transistor relative to a driver transistor forming part of the memory device based on a static noise margin value. A leakage reduction circuit and method includes reducing a voltage via a current leakage of a transistor to track the leakage of the memory cells and generating a sleep signal if the voltage drops below a predetermined threshold.
摘要翻译：用于增加存储器件的读取稳定性的装置和方法包括：基于静态噪声容限值，根据晶体管相对于形成存储器件的一部分的驱动晶体管的尺寸比来调整睡眠晶体管的尺寸。泄漏减少电路和方法包括通过晶体管的电流泄漏来降低电压以跟踪存储器单元的泄漏并且如果电压降低到预定阈值以下，则产生睡眠信号。

33. 发明授权

US07304903B2 Sense amplifier circuit 失效
标题翻译：感应放大电路
公开(公告)号：US07304903B2
公开(公告)日：2007-12-04
申请号：US11337348
申请日：2006-01-23
申请人： Saibal Mukhopadhyay , Hamid Mahmoodi , Kaushik Roy
发明人： Saibal Mukhopadhyay , Hamid Mahmoodi , Kaushik Roy
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C11/413
摘要： A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.
摘要翻译：读出放大器电路包括具有限定到电路的第一输入的第一栅极的第一双栅极金属氧化物半导体场效应晶体管（DGMOSFET），耦合到该电路的第一输出的第二栅极和输出端以及第二DGMOSFET 具有限定电路的第二输入的第一栅极，连接到第一DGMOSFET的输出的第二栅极和连接到第一DGMOSFET的第二栅极的输出端，第二DGMOSFET的输出耦合到第二DGMOSFET的第二输出端电路。

34. 发明申请

US20060220679A1 Low power scan design and delay fault testing technique using first level supply gating 失效
标题翻译：低功耗扫描设计和延时故障测试技术采用一级电源门控
公开(公告)号：US20060220679A1
公开(公告)日：2006-10-05
申请号：US11099386
申请日：2005-04-05
申请人： Swarup Bhunia , Hamid Mahmoodi , Arijit Raychowhury , Saibal Mukhopadhyay , Kaushik Roy
发明人： Swarup Bhunia , Hamid Mahmoodi , Arijit Raychowhury , Saibal Mukhopadhyay , Kaushik Roy
IPC分类号： H03K19/173
CPC分类号： G01R31/31858
摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.
摘要翻译：电路包括输入块和组合逻辑块。输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。锁存器直接连接到组合逻辑块的第一级门。组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。开关从第一级门断开电源和/或接地。这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。

35. 发明授权

US5515292A Circuit activity driven state assignment of FSMS implemented in CMOS for low power reliable operations 失效
标题翻译：在CMOS中实现的FSMS的电路活动驱动状态分配用于低功率可靠操作
公开(公告)号：US5515292A
公开(公告)日：1996-05-07
申请号：US129816
申请日：1993-09-29
申请人： Kaushik Roy , Sharat Prasad
发明人： Kaushik Roy , Sharat Prasad
IPC分类号： G06F17/50 , G06F15/00
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method for optimizing a circuit containing a finite state machine (FSM) based on transition density. A first state assignment is assigned for each state. Then, a first transition density characteristic associated with the first state assignment is determined and a second state assignment, different from said first state assignment is assigned for each state. A second transition density characteristic associated with the second state assignment is then determined and the first state assignment is set equal to the second state assignment if second transition density characteristic is less than a predetermined amount. The process is repeated until the transition density has been minimized.
摘要翻译：一种基于转换密度优化包含有限状态机（FSM）的电路的方法。为每个状态分配第一个状态赋值。然后，确定与第一状态分配相关联的第一转移密度特性，并且为每个状态分配与所述第一状态分配不同的第二状态分配。然后确定与第二状态分配相关联的第二转移密度特性，并且如果第二转移密度特性小于预定量，则将第一状态分配设置为等于第二状态分配。重复该过程直到转变密度最小化。

36. 发明授权

US5487017A Circuit activity driven multilevel logic optimization for low power reliable operation 失效
标题翻译：电路活动驱动的多电平逻辑优化用于低功率可靠运行
公开(公告)号：US5487017A
公开(公告)日：1996-01-23
申请号：US18984
申请日：1993-02-18
申请人： Sharat Prasad , Kaushik Roy
发明人： Sharat Prasad , Kaushik Roy
IPC分类号： G06F17/50 , H03M5/20 , H03M5/00
CPC分类号： G06F17/505 , H03M5/20 , G06F2217/78
摘要： A method and apparatus for optimizing a boolean network. The boolean network contains a plurality of functions and a plurality of nodes. Any cube-free divisors (a divisor in which no cube divides the divisor evenly) in the boolean network which apply to at least two of the functions are located (108). The greatest divisor, which is defined as the cube-free divisor which brings about the largest net savings, is determined (114). The net savings comprises both an area savings component and a power savings component. Once the greatest divisor is determined, it is replaced with a variable in each of the functions (116) and added to the boolean network as a new function to create an optimized boolean network (118).
摘要翻译：一种用于优化布尔网络的方法和装置。布尔网络包含多个功能和多个节点。在布尔网络中，至少有两个函数的任何无立方体的除数（其中没有立方体除数除数除数的除数）位于（108）。最大的除数被定义为无节数除数，产生最大的净储蓄，是确定的（114）。净节约包括面积节省部分和节电部分。一旦确定了最大的除数，它将被替换为每个函数（116）中的一个变量，并作为一个新的函数添加到布尔网络中，以创建优化的布尔网络（118）。

37. 发明申请

US20110282233A1 LOW-POWER REAL-TIME SEIZURE DETECTION SYSTEM 审中-公开
标题翻译：低功耗实时检测系统
公开(公告)号：US20110282233A1
公开(公告)日：2011-11-17
申请号：US13144452
申请日：2010-01-13
申请人： Shriram Raghunathan , Pedro Irazoqui , Sumeet Kumar Gupta , Kaushik Roy
发明人： Shriram Raghunathan , Pedro Irazoqui , Sumeet Kumar Gupta , Kaushik Roy
IPC分类号： A61B5/0476
CPC分类号： A61B5/0476 , A61B5/048 , A61B5/4094
摘要： A method for detecting an approaching seizure is disclosed. The method includes receiving an analog neurosignal from an electrode, comparing the analog neurosignal with a predetermined amplitude threshold to generate a plurality of digital transitions corresponding to the analog neurosignal transitioning from a first level below the predetermined amplitude threshold to a second level above the predetermined amplitude threshold, generating a plurality of comparator signals, each comparator signal of the plurality of comparator signals corresponding to a comparison of a length of time between a pair of digital transitions of the plurality of digital transitions and a predetermined temporal threshold, and generating a seizure detection signal if at least two of the comparator signals of the plurality of comparator signals are enabled. A seizure detection system for detecting an approaching seizure is also disclosed.
摘要翻译：公开了一种用于检测接近发作的方法。该方法包括从电极接收模拟神经信号，将模拟神经信号与预定幅度阈值进行比较，以产生对应于从预定幅度阈值以下的第一电平转换到高于预定幅度的第二电平的模拟神经信号转换的多个数字转变阈值，产生多个比较器信号，所述多个比较器信号的每个比较器信号对应于所述多个数字转换中的一对数字转换与预定时间阈值之间的时间长度的比较，并且产生检测检测信号，如果多个比较器信号中的至少两个比较器信号被使能。还公开了一种用于检测接近发作的缉获量检测系统。

38. 发明申请

US20110093781A1 DECLARATIVE TASK-BASED USER INTERFACES 有权
标题翻译：基于特定任务的用户界面
公开(公告)号：US20110093781A1
公开(公告)日：2011-04-21
申请号：US12722775
申请日：2010-03-12
申请人： Rahim Mohamed Yaseen , Jon Rexford Degenhardt , Sean Kevin Frogner , Sudhakar Kaki , Maria Elisabeth Kaval , Yee Wah Lee , Min Lu , Christopher Scott Nash , Kaushik Roy , Kanchan Shringi , Vipul Shroff , Yu Sui , Alvin H. To , Sanjin Tulac , Dejia Wang
发明人： Rahim Mohamed Yaseen , Jon Rexford Degenhardt , Sean Kevin Frogner , Sudhakar Kaki , Maria Elisabeth Kaval , Yee Wah Lee , Min Lu , Christopher Scott Nash , Kaushik Roy , Kanchan Shringi , Vipul Shroff , Yu Sui , Alvin H. To , Sanjin Tulac , Dejia Wang
IPC分类号： G06F3/01
CPC分类号： G06Q10/00
摘要： In one embodiment, a method for building wizard-style user interfaces (UIs) for a business task includes identifying a collection of metadata associated with the business task, and processing the collection of metadata to provide a set of wizard-style UIs pertaining to the business task.
摘要翻译：在一个实施例中，用于为业务任务构建向导风格的用户界面（UI）的方法包括标识与业务任务相关联的元数据集合，以及处理元数据集合以提供一组属于业务任务。

39. 发明授权

US07681133B2 Declarative task-based user interfaces 有权
标题翻译：基于声明的基于任务的用户界面
公开(公告)号：US07681133B2
公开(公告)日：2010-03-16
申请号：US11525985
申请日：2006-09-22
申请人： Rahim Mohamed Yaseen , Jon Rexford Degenhardt , Sean Kevin Frogner , Sudhakar Kaki , Maria Elisabeth Kaval , Yee Wah Lee , Min Lu , Christopher Scott Nash , Kaushik Roy , Kanchan Shringi , Vipul Shroff , Yu Sui , Alvin H. To , Sanjin Tulac , Dejia Wang
发明人： Rahim Mohamed Yaseen , Jon Rexford Degenhardt , Sean Kevin Frogner , Sudhakar Kaki , Maria Elisabeth Kaval , Yee Wah Lee , Min Lu , Christopher Scott Nash , Kaushik Roy , Kanchan Shringi , Vipul Shroff , Yu Sui , Alvin H. To , Sanjin Tulac , Dejia Wang
IPC分类号： G06F3/00 , G06F9/44
CPC分类号： G06Q10/00
摘要： In one embodiment, a method for building wizard-style user interfaces (UIs) for a business task includes identifying a collection of metadata associated with the business task, and processing the collection of metadata to provide a set of wizard-style UIs pertaining to the business task.
摘要翻译：在一个实施例中，用于为业务任务构建向导风格的用户界面（UI）的方法包括标识与业务任务相关联的元数据集合，以及处理元数据集合以提供一组属于业务任务。

40. 发明授权

US07672152B1 Memory cell with built-in process variation tolerance 有权
标题翻译：具有内置过程变化公差的存储单元
公开(公告)号：US07672152B1
公开(公告)日：2010-03-02
申请号：US12038314
申请日：2008-02-27
申请人： Jaydeep P. Kulkarni , Kaushik Roy
发明人： Jaydeep P. Kulkarni , Kaushik Roy
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C11/412
摘要： A Schmitt Trigger (ST) based, fully differential, 10-transistor (10T) SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The Schmitt trigger based bitcell achieves 1.56× higher read static noise margin (SNM) (VDD=400 mV) compared to a conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. The 10T bitcell has two cross-coupled Schmitt trigger inverters which each consist of four transistors, including a PMOS transistor and two NMOS transistors in series, and an NMOS feedback transistor which is connected between the inverter output and the junction between the series-connected NMOS transistors. Each inverter has one associated NMOS access transistor.
摘要翻译：基于施密特触发（ST）的全差分10晶体管（10T）SRAM（静态随机存取存储器）位元，适用于子阈值操作。与传统的6T电池相比，基于施密特触发的位单元实现了1.56倍的读取静态噪声容限（SNM）（VDD = 400 mV）。基于稳定的施密特触发器的存储单元展现了内置的工艺变化公差，可以在整个过程角落提供紧密的SNM分布。它利用完全差分操作，因此不需要来自当前6T架构的任何架构更改。 10T位单元具有两个交叉耦合施密特触发器反相器，每个反相器由四个晶体管组成，包括PMOS晶体管和两个串联的NMOS晶体管，NMOS反馈晶体管连接在反相器输出端和串联NMOS晶体管晶体管。每个逆变器都有一个相关的NMOS存取晶体管。

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