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31. 发明申请

WO2008118949A1 A SYSTEM AND METHOD FOR EXECUTING INSTRUCTIONS PRIOR TO AN EXECUTION STAGE IN A PROCESSOR 审中-公开
标题翻译：在处理器中执行执行阶段的指令的系统和方法
公开(公告)号：WO2008118949A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/058246
申请日：2008-03-26
申请人： QUALCOMM INCORPORATED , SETH, Kiran , DIEFFENDERFER, James, Norris , MCLLVAINE, Michael, Scott , NUNAMAKER, Nathan
发明人： SETH, Kiran , DIEFFENDERFER, James, Norris , MCLLVAINE, Michael, Scott , NUNAMAKER, Nathan
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to the execution stage within the processor. Partially or wholly executing the instruction prior to the execution stage in the pipeline speeds up the execution of the instruction and allows the processor to more effectively utilize its resources, thus increasing the processor's efficiency.
摘要翻译：公开了一种在流水线处理器内的多个流水线级中处理多个指令的方法。该方法在流水线级中部分或全部地执行停止的指令，其在处理器内的执行阶段之前具有不同于指令执行的功能。在流水线执行阶段之前部分或全部执行指令可加速指令的执行，并允许处理器更有效地利用其资源，从而提高处理器的效率。

32. 发明申请

WO2008098140A1 ADDRESS TRANSLATION METHOD AND APPARATUS 审中-公开
标题翻译：地址转换方法和装置
公开(公告)号：WO2008098140A1
公开(公告)日：2008-08-14
申请号：PCT/US2008/053338
申请日：2008-02-07
申请人： QUALCOMM Incorporated , KOPEC, Brian Joseph , AUGSBURG, Victor Roberts , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： KOPEC, Brian Joseph , AUGSBURG, Victor Roberts , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F12/04
CPC分类号： G06F12/04 , G06F12/1027 , G06F2212/655 , Y02D10/13
摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.
摘要翻译：通过识别导致存储器中的不同页面之间的边界交叉的地址以及链接与两个存储器页面相关联的地址转换信息来改进处理器内的地址转换性能。根据处理器的一个实施例，处理器包括被配置为识别对跨越第一和第二存储器页之间的页边界的存储区的访问的电路。电路还被配置为链接与第一和第二存储器页相关联的地址转换信息。因此，响应于后续访问相同的存储器区域，可以基于单个地址转换来检索与第一和第二存储器页面相关联的地址转换信息。

33. 发明申请

WO2008092037A1 USE OF REGISTER RENAMING SYSTEM FOR FORWARDING INTERMEDIATE RESULTS BETWEEN CONSTITUENT INSTRUCTIONS OF AN EXPANDED INSTRUCTION 审中-公开
标题翻译：使用注册登记系统，用于在扩展指令的综合指示之间进行中间结果
公开(公告)号：WO2008092037A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/051958
申请日：2008-01-24
申请人： QUALCOMM INCORPORATED , MCLLVAINE, Michael, Scott , DIEFFENDERFER, James, Norris , NUNAMAKER, Nathan, Samuel , SARTORIUS, Thomas, Andrew , SMITH, Rodney, Wayne
发明人： MCLLVAINE, Michael, Scott , DIEFFENDERFER, James, Norris , NUNAMAKER, Nathan, Samuel , SARTORIUS, Thomas, Andrew , SMITH, Rodney, Wayne
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3017 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename table, and writes intermediate results to the identified physical register. A second constituent instruction performs a look up in the constituent instruction rename table and reads the intermediate results from the physical register. Constituent instruction rename logic tracks the constituent instructions through the pipeline, and delete the constituent instruction rename table entry and returns the PRN to a free list when the second constituent instruction has read the intermediate results.
摘要翻译：使用寄存器重命名资源和控制逻辑，在扩展指令的组成指令之间传递中间结果。第一组成指令生成中间结果，并在组成指令重命名表中分配PRN，并将中间结果写入所识别的物理寄存器。第二个组成指令在组成指令重命名表中执行查询，并从物理寄存器读取中间结果。组成指令重命名逻辑通过流水线跟踪组成指令，并删除组成指令重命名表项，并在第二组成指令读取中间结果时将PRN返回到空闲列表。

34. 发明申请

WO2008028103A3 METHODS AND APPARATUS FOR EMULATING THE BRANCH PREDICTION BEHAVIOR OF AN EXPLICIT SUBROUTINE CALL 审中-公开
标题翻译：用于模拟显式子程序呼叫的分支预测行为的方法和设备
公开(公告)号：WO2008028103A3
公开(公告)日：2008-05-29
申请号：PCT/US2007077340
申请日：2007-08-31
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN , SARTORIUS THOMAS ANDREW , SMITH WAYNE
发明人： DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN , SARTORIUS THOMAS ANDREW , SMITH WAYNE
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3005 , G06F9/30058 , G06F9/30101 , G06F9/322 , G06F9/3806
摘要： An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
摘要翻译：公开了一种用于模拟显式子例程调用的分支预测行为的装置。该装置包括被配置为接收指令地址和第二输入的第一输入。第二输入被配置为接收将指令地址描述为与对子例程的隐式子例程调用相关的预解码信息。响应于预解码信息，该装置还包括加法器，该加法器被配置为向定义返回地址的指令地址添加常数，使得返回地址被存储到显式子例程资源，从而便于后续分支预测返回呼叫指令。

35. 发明申请

WO2008055045A1 A SYSTEM AND METHOD FOR USING A WORKING GLOBAL HISTORY REGISTER 审中-公开
标题翻译：一种使用工作全球历史寄存器的系统和方法
公开(公告)号：WO2008055045A1
公开(公告)日：2008-05-08
申请号：PCT/US2007/082538
申请日：2007-10-25
申请人： QUALCOMM INCORPORATED , STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
发明人： STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3804 , G06F9/3806 , G06F9/3861
摘要： A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register, wherein the first register. The method further loads the branch history information into the second register during the second pipeline stage.
摘要翻译：公开了处理分支历史信息的方法。该方法从指令高速缓存中检索分支指令，并在多个流水线级中执行分支指令。该方法验证分支指令已被识别。该方法还在第一流水线阶段期间接收分支历史信息，并将分支历史信息加载到第一寄存器中，其中第一寄存器。该方法在第二流水线阶段期间进一步将分支历史信息加载到第二寄存器中。

36. 发明申请

WO2007143508A2 SLIDING-WINDOW, BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：滑动窗口，基于块的分支目标地址高速缓存
公开(公告)号：WO2007143508A2
公开(公告)日：2007-12-13
申请号：PCT/US2007/070111
申请日：2007-05-31
申请人： QUALCOMM Incorporated , SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SARTORIUS, Thomas Andrew
发明人： SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3844
摘要： A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
摘要翻译：滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签第一个指令在块中。这些块各自对应于从存储器获取的一组指令，例如I缓存。在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。滑动窗口，基于块的BTAC允许存储落在相同指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

37. 发明申请

WO2006130466A3 A METHOD AND APPARATUS FOR PREDICTING BRANCH INSTRUCTIONS 审中-公开
标题翻译：一种用于预测分支指令的方法和装置
公开(公告)号：WO2006130466A3
公开(公告)日：2007-11-22
申请号：PCT/US2006020440
申请日：2006-05-24
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
发明人： SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
IPC分类号： G06F9/42
CPC分类号： G06F9/3844
摘要： A microprocessor (10) includes two branch history tables, and is configured to use a first one (48) of the branch history tables for predicting branch instructions that are hits in a branch target cache (46), and to use a second one (50) of the branch history tables for predicting branch instructions that are misses in the branch target cache (46). As such, the first branch history table (48) is configured to have an access speed matched to that of the branch target cache (46), so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table (50) thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器（10）包括两个分支历史表，并且被配置为使用分支历史表中的第一个（48）来预测分支目标高速缓存（46）中的命中的分支指令，并且使用第二个分支指令 50）用于预测分支目标高速缓存（46）中未命中的分支指令的分支历史表。因此，第一分支历史表（48）被配置为具有与分支目标高速缓存（46）的访问速度相匹配的访问速度，使得其预测信息相对于可能发生的早期的分支目标高速缓存命中检测而及时可用在微处理器的指令管道中。因此，第二分支历史表（50）仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

38. 发明申请

WO2007109631A2 REPRESENTING LOOP BRANCHES IN A BRANCH HISTORY REGISTER WITH MULTIPLE BITS 审中-公开
标题翻译：在分支机构历史记录中表示环路分支与多个位
公开(公告)号：WO2007109631A2
公开(公告)日：2007-09-27
申请号：PCT/US2007064331
申请日：2007-03-19
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , RYCHLIK BOHUSLAV
发明人： DIEFFENDERFER JAMES NORRIS , RYCHLIK BOHUSLAV
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： In response to a property of a conditional branch instruction associated with a loop, such as a property indicating that the branch is a loop-ending branch, a count of the number of iterations of the loop is maintained, and a multi-bit value indicative of the loop iteration count is stored in a Branch History Register (BHR). In one embodiment, the multi-bit value may comprise the actual loop count, in which case the number of bits is variable. In another embodiment, the number of bits is fixed (e.g., two) and loop iteration counts are mapped to one of a fixed number of multi-bit values (e.g., four) by comparison to thresholds. Separate iteration counts may be maintained for nested loops, and a multi-bit value stored in the BHR may indicate a loop iteration count of only an inner loop, only the outer loop, or both.
摘要翻译：响应于与循环相关联的条件转移指令的属性，例如指示分支是循环结束分支的属性，维持循环的迭代次数的计数，并且指示多位值循环迭代计数存储在分支历史记录寄存器（BHR）中。在一个实施例中，多比特值可以包括实际循环计数，在这种情况下，比特数是可变的。在另一个实施例中，比特数是固定的（例如，两个），并且与阈值相比较，循环迭代计数被映射到固定数量的多比特值（例如，四）中的一个。对于嵌套循环可以保持单独的迭代计数，并且存储在BHR中的多位值可能仅表示内部循环，仅外部循环或两者的循环迭代计数。

39. 发明申请

WO2007090175A1 CACHE LOCKING WITHOUT INTERFERENCE FROM NORMAL ALLOCATION 审中-公开
标题翻译：缓存锁定，与正常分配无干扰
公开(公告)号：WO2007090175A1
公开(公告)日：2007-08-09
申请号：PCT/US2007/061415
申请日：2007-01-31
申请人： QUALCOMM INCORTPORATED , AUGSBURG, Victor Roberts , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SARTORIUS, Thomas Andrew
发明人： AUGSBURG, Victor Roberts , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SARTORIUS, Thomas Andrew
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F9/30047 , G06F9/3824
摘要： A Block Normal Cache Allocation (BNCA) mode is defined for a processor. In BNCA mode, cache entries may only be allocated by predetermined instructions. Normal memory access instructions (for example, as part of interrupt code) may execute and will retrieve data from main memory in the event of a cache miss; however, these instructions are not allowed to allocate entries in the cache. Only the predetermined instructions (for example, those used to establish locked cache entries) may allocate entries in the cache. When the locked entries are established, the processor exits BNCA mode, and any memory access instruction may allocate cache entries. BNCA mode may be indicated by setting a bit in a configuration register.
摘要翻译：为处理器定义块正常缓存分配（BNCA）模式。在BNCA模式下，缓存条目只能由预定的指令分配。正常存储器访问指令（例如，作为中断代码的一部分）可以执行并且将在高速缓存未命中的情况下从主存储器检索数据; 但是，这些指令不允许在缓存中分配条目。只有预定的指令（例如，用于建立锁定高速缓存条目的指令）可以在高速缓存中分配条目。当锁定的条目建立时，处理器退出BNCA模式，任何存储器访问指令都可以分配高速缓存条目。可以通过在配置寄存器中设置位来指示BNCA模式。

40. 发明申请

WO2007085010A2 EARLY CONDITIONAL SELECTION OF AN OPERAND 审中-公开
标题翻译：一项业务的早期条件选择
公开(公告)号：WO2007085010A2
公开(公告)日：2007-07-26
申请号：PCT/US2007060814
申请日：2007-01-22
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , MCILVAINE MICHAEL SCOTT , SARTORIUS THOMAS ANDREW
发明人： DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , MCILVAINE MICHAEL SCOTT , SARTORIUS THOMAS ANDREW
CPC分类号： G06F9/30072 , G06F9/30036 , G06F9/30094 , G06F9/3016 , G06F9/30167
摘要： Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.
摘要翻译：由于等待不会被选择操作数指令使用的操作数而导致的延迟基于早期认识到，为了完成选择操作数指令的处理不需要这种操作数数据而得到缓解。在执行之前的适当点处，确定选择操作数指令所指定的选择标准或标准，影响选择标准的条件以及操作数的可用性。保持电路使用这些确定来控制控制处理器管线失速的保持信号的激活和释放。如果所选择的操作数可用，即使另一个不被使用的操作数不可用，也可以跳过等待操作数数据所需的停顿或提前终止停顿。由于等待操作数而停顿，直到满足选择标准并且选取的操作数被提取并使其可用。

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