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31. 发明授权

US5870046A Analog isolation system with digital communication across a capacitive barrier 失效
公开(公告)号：US5870046A
公开(公告)日：1999-02-09
申请号：US837702
申请日：1997-04-22
申请人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
发明人： Jeffrey W. Scott , Navdeep S. Sooch , David R. Welland
IPC分类号： H04B14/06 , H04L7/033 , H04L25/06 , H04M11/06 , H03M3/02
CPC分类号： H04B14/062 , H04L25/0266 , H04L25/06 , H04M11/06 , H04L7/033
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

32. 发明授权

US5594751A Current-apertured vertical cavity laser 失效
标题翻译：电流孔径垂直腔激光器
公开(公告)号：US5594751A
公开(公告)日：1997-01-14
申请号：US494823
申请日：1995-06-26
申请人： Jeffrey W. Scott
发明人： Jeffrey W. Scott
IPC分类号： H01S5/00 , H01S5/042 , H01S5/183 , H01S5/22 , H01S3/19
CPC分类号： H01S5/18333 , H01S2301/166 , H01S5/18311 , H01S5/18316 , H01S5/1833 , H01S5/18358
摘要： A vertical-cavity surface-emitting laser (VCSEL) has an active region, first and second mirror stacks forming a resonant cavity with a radial variation in index forming a transverse optical mode, and a thin insulating slot within the cavity to constrict the current to a diameter less than the beam waist of the optical mode thereby improving device efficiency and preferentially supporting single mode operation. In one embodiment, an insulating slot is formed by etching or selectively oxidizing a thin aluminum-containing semiconductor layer in towards the center of a cylindrical mesa. The slot thickness is sufficiently thin that the large index discontinuity has little effect on the transverse optical-mode pattern. The slot may be placed near an axial standing-wave null to minimize the perturbation of the index discontinuity and allow the use of thicker slots. In a preferred embodiment, the current constriction, formed by the insulating slot, is located on the p-type side of the active region and has a diameter significantly less than the beam waist of the optical mode, thus minimizing outward diffusion of carriers and ensuring single transverse-mode operation of the laser by suppressing spatial hole burning.
摘要翻译：垂直腔表面发射激光器（VCSEL）具有有源区域，形成谐振腔的第一和第二反射镜叠层具有形成横向光学模式的折射率的径向变化，以及腔内的薄绝缘槽，以将电流收缩直径小于光学模式的光束腰部，从而提高器件效率并优先支持单模操作。在一个实施例中，通过蚀刻或选择性地将薄的含铝半导体层朝向圆柱形台面的中心形成绝缘槽。狭缝厚度足够薄，使得大的折射率不连续性对横向光学模式图案几乎没有影响。槽可以放置在轴向驻波零点附近，以最小化指数不连续性的扰动，并允许使用较厚的槽。在优选实施例中，由绝缘槽形成的电流收缩部位于有源区域的p型侧，并且具有明显小于光学模式的光束腰部的直径，从而最小化载体的向外扩散并确保通过抑制空穴燃烧，激光的单横模操作。

33. 发明授权

US5016012A Technique for compensating switched capacitor circuits having gain-setting resistors 失效
标题翻译：用于补偿具有增益设定电阻的开关电容电路的技术
公开(公告)号：US5016012A
公开(公告)日：1991-05-14
申请号：US416888
申请日：1989-10-04
申请人： Jeffrey W. Scott , Thayamkulangara R. Viswanathan
发明人： Jeffrey W. Scott , Thayamkulangara R. Viswanathan
IPC分类号： H03M1/66 , H03H19/00 , H03M1/06 , H03M1/74 , H03M1/80
CPC分类号： H03M1/0604 , H03M1/804
摘要： A technique for compensating for variations in a resistor set overall gain switched-capacitor circuits, such as high accuracy digital-to-analog converters. The variation in overall gain from the desired gain is due to the variation in the total capacitance of the capacitors, compared to the variation in the resistance of the resistor, in the circuit during manufacture. A bias circuit, with two reference voltage outputs, is adapted to have a capacitor and a fixed resistor vary one of the voltage references depending on the capacitance thereof. The voltage difference between the two voltage references varies the overall gain of the switched capacitor circuit to compensate for variations in the overall gain. Also, a switched-capacitor digital-to-analog converter utilizing the above technique is presented.

34. 发明授权

US09304773B2 Data processor having dynamic control of instruction prefetch buffer depth and method therefor 有权
标题翻译：数据处理器具有指令预取缓冲区深度的动态控制及其方法
公开(公告)号：US09304773B2
公开(公告)日：2016-04-05
申请号：US11385463
申请日：2006-03-21
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/38 , G06F9/30 , G06F12/08
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/3814 , G06F12/0862 , G06F2212/6022 , Y02D10/13
摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).
摘要翻译：数据处理器（102）包括预取缓冲器（112）和获取控制单元（116）。预取缓冲器（112）具有多条线。预取缓冲器（112）具有可变的最大深度，其定义能够存储指令的多行的行数。获取控制单元（116）耦合到预取缓冲器以监视预取缓冲器（112）的多行中的至少一行并且响应于预取缓冲器（112）的状态来调整预取缓冲器（112）的可变最大深度数据处理器（102）。

35. 发明授权

US09223678B2 Data processor device having a debug control module which selectively modifies trace messages 有权
标题翻译：具有调试控制模块的数据处理器设备，其选择性地修改跟踪消息
公开(公告)号：US09223678B2
公开(公告)日：2015-12-29
申请号：US13955102
申请日：2013-07-31
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F11/30 , G06F11/36
CPC分类号： G06F11/36 , G06F11/3072 , G06F11/3082 , G06F11/3636
摘要： Upon detecting an occurrence of a watchpoint event for debugging a computer processing system, at least a portion of at least one message in a trace message buffer is flushed when a characteristic of the at least one of the messages matches a specified characteristic.
摘要翻译：当检测到用于调试计算机处理系统的观察点事件的发生时，当所述至少一个消息的特性与指定的特性匹配时，跟踪消息缓冲器中的至少一个消息的至少一部分被刷新。

36. 发明授权

US09069896B2 Data processor device for handling a watchpoint and method thereof 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US09069896B2
公开(公告)日：2015-06-30
申请号：US13598240
申请日：2012-08-29
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/3636
摘要： During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.
摘要翻译：在数据处理器的调试操作模式期间，在数据处理器确定观察点事件已经发生，并且作为响应，存储跟尚未传送到调试器的跟踪信息的跟踪FIFO的操作条件被改变。例如，FIFO追查观察点的发生导致跟踪信息在跟踪信息已被传送到跟踪分析器之前被从跟踪FIFO刷新。

37. 发明申请

US20150039870A1 SYSTEMS AND METHODS FOR LOCKING BRANCH TARGET BUFFER ENTRIES 有权
标题翻译：用于锁定分支目标缓冲区入口的系统和方法
公开(公告)号：US20150039870A1
公开(公告)日：2015-02-05
申请号：US13955106
申请日：2013-07-31
申请人： JEFFREY W. SCOTT , William C. Moyer
发明人： JEFFREY W. SCOTT , William C. Moyer
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.
摘要翻译：数据处理系统包括被配置为执行处理器指令的处理器和具有多个条目的分支目标缓冲器。每个条目被配置为存储分支目标地址和锁定指示符，其中所述锁定指示符指示所述条目是否是替换的候选，并且其中所述处理器被配置为在所述处理器指令的执行期间访问所述分支目标缓冲器。数据处理系统还包括配置成确定分支目标缓冲器的饱和度水平的控制电路，其中响应于饱和度达到饱和阈值，控制电路被配置为断言多个条目，以指示所述多个条目中的一个或多个条目不是替换候选者。

38. 发明授权

US08769355B2 Using built-in self test for preventing side channel security attacks on multi-processor systems 有权
标题翻译：使用内置的自检来防止多处理器系统的侧面通道安全攻击
公开(公告)号：US08769355B2
公开(公告)日：2014-07-01
申请号：US13169664
申请日：2011-06-27
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G11C29/00
CPC分类号： G06F21/755
摘要： A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which performs BIST memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
摘要翻译：一种具有第一处理器，第二处理器，第二处理器的本地存储器和第二处理器的内置自检（BIST）控制器的数据处理系统，其对第二处理器的本地存储器执行BIST存储器访问并且包括随机值生成器。该系统可以执行包括由第一处理器执行安全代码序列并且由第二处理器的BIST控制器响应于随机值生成器对第二处理器的本地存储器进行BIST存储器访问的方法。执行BIST存储器访问同时执行安全代码序列。

39. 发明申请

US20140053003A1 RANDOM TIMESLOT CONTROLLER FOR ENABLING BUILT-IN SELF TEST MODULE 有权
标题翻译：随机时间控制器，用于启动内置自检模块
公开(公告)号：US20140053003A1
公开(公告)日：2014-02-20
申请号：US13589580
申请日：2012-08-20
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F21/02 , G06F1/00
CPC分类号： G06F21/558 , G06F21/556 , G06F21/755
摘要： A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
摘要翻译：一种具有第一处理器，第二处理器，第二处理器的本地存储器和第二处理器的内置自检（BIST）控制器的数据处理系统，其可以被随机地启用以对本地存储器执行存储器访问的第二处理器，并且包括随机值发生器。该系统可以执行包括由第一处理器执行安全代码序列并且由第二处理器的BIST控制器响应于随机值生成器对第二处理器的本地存储器进行BIST存储器访问的方法。执行BIST存储器访问同时执行安全代码序列。

40. 发明申请

US20140052922A1 RANDOM ACCESS OF A CACHE PORTION USING AN ACCESS MODULE 有权
标题翻译：使用访问模块对缓存部分进行随机访问
公开(公告)号：US20140052922A1
公开(公告)日：2014-02-20
申请号：US13690888
申请日：2012-11-30
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/0802 , G11C5/14 , G11C7/24 , G11C29/12 , Y02D10/13
摘要： A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
摘要翻译：一种具有第一处理器，第二处理器，第二处理器的本地存储器和第二处理器的内置自检（BIST）控制器的数据处理系统，其可以被随机地启用以对本地存储器执行存储器访问的第二处理器，并且包括随机值发生器。该系统可以执行包括由第一处理器执行安全代码序列并且由第二处理器的BIST控制器响应于随机值生成器对第二处理器的本地存储器进行BIST存储器访问的方法。执行BIST存储器访问同时执行安全代码序列。

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