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31. 发明申请

US20050117406A1 Semiconductor integrated circuit device with main cell array and fuse cell array 失效
标题翻译：具有主单元阵列和熔丝单元阵列的半导体集成电路器件
公开(公告)号：US20050117406A1
公开(公告)日：2005-06-02
申请号：US11033398
申请日：2005-01-12
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
摘要翻译：半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。熔丝单元字线形成在与主单元字线的方向相同的方向上。

32. 发明授权

US06560144B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06560144B2
公开(公告)日：2003-05-06
申请号：US10086869
申请日：2002-03-04
申请人： Shigeru Atsumi , Hironori Banba
发明人： Shigeru Atsumi , Hironori Banba
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C16/08
摘要： A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of OV or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor, and a source-to-drain current path of the second P-channel MOS transistor is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor.
摘要翻译：非易失性半导体存储器件包括具有第一和第二N沟道MOS晶体管的行解码器电路和对应于每条字线的第一和第二P沟道MOS晶体管。第一N沟道MOS晶体管的源极 - 漏极电流路径的一端连接到字线，并且其另一端连接到预解码器电路的对应的一个输出端。第二N沟道MOS晶体管的源极 - 漏极电流路径的一端连接到字线，并且其另一端在数据擦除模式下被提供0V以上的电压，并被提供有低数据擦除模式以外的模式下的低逻辑电平信号。第一P沟道MOS晶体管的源极 - 漏极电流路径并联连接到第一N沟道MOS晶体管的源极 - 漏极电流路径，并且第二P沟道MOS晶体管的源极 - 漏极电流路径 P沟道MOS晶体管与第二N沟道MOS晶体管的源极 - 漏极电流路径并联连接。

33. 发明授权

US06498761B2 Power supply circuit and semiconductor memory device having the same 失效
公开(公告)号：US06498761B2
公开(公告)日：2002-12-24
申请号：US09983258
申请日：2001-10-23
申请人： Hironori Banba , Shigeru Atsumi
发明人： Hironori Banba , Shigeru Atsumi
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C5/145 , H02M3/073
摘要： A number of booster circuits to be operated out of a plurality of booster circuits are selected in accordance with a level of the boosted voltage to be provided at a common voltage output terminal of the plurality of booster circuits. With such an arrangement, fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of the booster circuits can be effectively reduced to make the semiconductor memory device driven by the power supply circuit operate reliably. Further, one of the output terminals of intermediate voltage booster circuits is connected to the output terminal of a high voltage booster circuit. Then, a desired voltage can be obtained from the booster circuits that are implemented without using costly transistors to reduce the chip cost.

34. 发明授权

US06323630B1 Reference voltage generation circuit and reference current generation circuit 有权
标题翻译：参考电压发生电路和参考电流产生电路
公开(公告)号：US06323630B1
公开(公告)日：2001-11-27
申请号：US09604816
申请日：2000-06-28
申请人： Hironori Banba
发明人： Hironori Banba
IPC分类号： G05F316
CPC分类号： G05F3/242 , G05F3/245 , G05F3/247
摘要： A reference voltage generation circuit includes a first current conversion circuit for converting a forward voltage of a p-n junction into a first current proportional to the forward voltage, a second current conversion circuit for converting a voltage difference between forward voltages of p-n junctions differing in current density into a second current proportional to the voltage difference, a current add circuit for adding the first current from the first current conversion circuit to the second current from the second current conversion circuit, and a current-to-voltage conversion circuit for converting a third current into a voltage. MIS transistors are used as active elements other than the p-n junctions. This enables the less temperature-dependent, less power-supply-voltage-dependent output voltage of the reference voltage generation circuit to be set at a given value in the range of the power supply voltage, which enables semiconductor devices to operate on 1.25V or lower.
摘要翻译：参考电压产生电路包括：第一电流转换电路，用于将pn结的正向电压转换成与正向电压成比例的第一电流;第二电流转换电路，用于转换电流密度不同的pn结的正向电压之间的电压差成为与电压差成比例的第二电流，用于将来自第一电流转换电路的第一电流与来自第二电流转换电路的第二电流相加的电流加法电路，以及用于转换第三电流的电流 - 电压转换电路变成电压。 MIS晶体管用作p-n结以外的有源元件。这使得参考电压产生电路的温度依赖性较小的电源电压依赖输出电压被设定在电源电压范围内的给定值，这使得半导体器件能够在1.25V或降低。

35. 发明授权

US6160391A Reference voltage generation circuit and reference current generation circuit 失效
标题翻译：参考电压发生电路和参考电流产生电路
公开(公告)号：US6160391A
公开(公告)日：2000-12-12
申请号：US122641
申请日：1998-07-27
申请人： Hironori Banba
发明人： Hironori Banba
IPC分类号： G05F3/30 , G05F1/10 , G05F3/24 , G05F3/16 , H02M7/00
CPC分类号： G05F3/242 , G05F3/245 , G05F3/247
摘要： A reference voltage generation circuit includes a first current conversion circuit for converting a forward voltage of a p-n junction into a first current proportional to the forward voltage, a second current conversion circuit for converting a voltage difference between forward voltages of p-n junctions differing in current density into a second current proportional to the voltage difference, a current add circuit for adding the first current from the first current conversion circuit to the second current from the second current conversion circuit, and a current-to-voltage conversion circuit for converting a third current into a voltage. MIS transistors are used as active elements other than the p-n junctions. This enables the less temperature-dependent, less power-supply-voltage-dependent output voltage of the reference voltage generation circuit to be set at a given value in the range of the power supply voltage, which enables semiconductor devices to operate on 1.25V or lower.
摘要翻译：参考电压产生电路包括：第一电流转换电路，用于将pn结的正向电压转换成与正向电压成比例的第一电流;第二电流转换电路，用于转换电流密度不同的pn结的正向电压之间的电压差成为与电压差成比例的第二电流，用于将来自第一电流转换电路的第一电流与来自第二电流转换电路的第二电流相加的电流加法电路，以及用于转换第三电流的电流 - 电压转换电路变成电压。 MIS晶体管用作p-n结以外的有源元件。这使得参考电压产生电路的温度依赖性较小的电源电压依赖的输出电压被设定在电源电压范围内的给定值，这使得半导体器件能够在1.25V或降低。

36. 发明授权

US6128242A Power supply circuit and semiconductor memory device having the same 失效
公开(公告)号：US6128242A
公开(公告)日：2000-10-03
申请号：US30914
申请日：1998-02-26
申请人： Hironori Banba , Shigeru Atsumi
发明人： Hironori Banba , Shigeru Atsumi
IPC分类号： G11C16/06 , G11C5/14 , G11C16/30 , H02M3/07 , G11C7/00
CPC分类号： G11C16/30 , G11C5/145 , H02M3/073
摘要： A number of booster circuits to be operated out of a plurality of booster circuits are selected in accordance with a level of the boosted voltage to be provided at a common voltage output terminal of the plurality of booster circuits. With such an arrangement, fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of the booster circuits can be effectively reduced to make the semiconductor memory device driven by the power supply circuit operate reliably. Further, one of the output terminals of intermediate voltage booster circuits is connected to the output terminal of a high voltage booster circuit. Then, a desired voltage can be obtained from the booster circuits that are implemented without using costly transistors to reduce the chip cost.

37. 发明授权

US6108246A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US6108246A
公开(公告)日：2000-08-22
申请号：US391153
申请日：1999-09-08
申请人： Akira Umezawa , Hitoshi Shiga , Hironori Banba , Shigeru Atsumi
发明人： Akira Umezawa , Hitoshi Shiga , Hironori Banba , Shigeru Atsumi
IPC分类号： G11C11/413 , G11C5/14 , G11C7/10 , G11C16/06 , G11C16/30 , G11C29/04 , H01L21/82 , H01L21/822 , H01L27/04 , G11C11/40
CPC分类号： G11C16/30 , G11C5/147 , G11C7/1045
摘要： A nonvolatile memory semiconductor memory device is disclosed which incorporates fuse-cells in which data for setting a mode and redundancy data are stored. The nonvolatile memory semiconductor memory device incorporates a fuse-cell circuit including fuse-cells, a fuse-cell controlling circuit for reading data stored in the fuse-cell, a voltage boosting circuit for generating a boosted voltage and a voltage converting circuit which uses a reference voltage to convert the boosted voltage into read voltage for use when data is read from the fuse-cell. The reference voltage is generated by using a threshold voltage of a reference cell having the same structure as that of the fuse-cell.
摘要翻译：公开了一种非易失性存储器半导体存储器件，其包括熔丝单元，其中存储用于设置模式和冗余数据的数据。非易失性存储器半导体存储器件包括熔丝单元电路，其包括熔丝单元，用于读取存储在熔丝单元中的数据的熔丝单元控制电路，用于产生升压电压的升压电路和使用参考电压将升压电压转换为读电压，以便在从熔丝单元读取数据时使用。参考电压通过使用具有与熔丝单元相同结构的参考单元的阈值电压来产生。

38. 发明授权

US6034567A Semiconductor integrated circuit device provided with a differential amplifier 失效
标题翻译：具有差分放大器的半导体集成电路器件
公开(公告)号：US6034567A
公开(公告)日：2000-03-07
申请号：US30776
申请日：1998-02-26
申请人： Akira Umezawa , Shigeru Atsumi , Norihisa Arai , Hironori Banba , Ryo Sudo
发明人： Akira Umezawa , Shigeru Atsumi , Norihisa Arai , Hironori Banba , Ryo Sudo
IPC分类号： G11C11/419 , G05F3/24 , G05F3/30 , G11C11/409 , G11C11/413 , H01L21/8234 , H01L27/088 , H03F3/45 , H03F3/14
CPC分类号： H03F3/45479
摘要： A differential amplifier comprises an n-channel MOS transistor to the gate of which an input voltage VIN1 is fed, and an n-channel MOS transistor to the gate of which an input voltage VIN2 is fed. A p-channel MOS transistor arranged in such a manner that, to the source thereof, a power source voltage Vcc is fed, and the gate and drain thereof are connected to the drain of the MOS transistor, and a p-channel MOS transistor arranged in such a manner that the gate thereof is connected to the drain of the MOS transistor, the drain thereof is connected to the drain of the MOS transistor, and the voltage at this drain is outputted as an output voltage VOUT, and the output current I of a constant-current source is set so that the transistors constituting a differential amplifier may operate in a weak inversion zone.
摘要翻译：差分放大器包括输入电压VIN1的栅极的n沟道MOS晶体管和馈入输入电压VIN2的栅极的n沟道MOS晶体管。一个p沟道MOS晶体管，以这样一种方式被布置：从源极输入电源电压Vcc，其栅极和漏极连接到MOS晶体管的漏极，并配置有p沟道MOS晶体管以其栅极连接到MOS晶体管的漏极，其漏极连接到MOS晶体管的漏极，并且该漏极处的电压作为输出电压VOUT输出，并且输出电流I 设置恒流源，使得构成差分放大器的晶体管可以在弱反转区域中工作。

39. 发明授权

US6031397A Negative voltage detection circuit offsetting fluctuation of detection level 失效
标题翻译：负电压检测电路抵消检测水平的波动
公开(公告)号：US6031397A
公开(公告)日：2000-02-29
申请号：US28275
申请日：1998-02-24
申请人： Hironori Banba
发明人： Hironori Banba
IPC分类号： G01R19/00 , G01R19/165 , G11C5/14 , G11C11/408 , G11C16/06 , G11C16/30 , H02M3/07 , H03K5/08 , H03K5/153
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H03K5/08 , G01R19/16576
摘要： A negative voltage detection circuit has a detection level of which is independent from the threshold voltage of a MOS transistor incorporated into the memory device. The negative voltage detection circuit detects whether or not the output voltage of a charge pump has a desired level, and then a signal is output in accordance with the detection result. The negative voltage detection circuit detects the negative voltage by comparing the multiple of the negative voltage by -(1/n) (n is a natural number) with a the positive inner reference voltage V.sub.ref. When the multiple and the reference voltage V.sub.ref are equal to each other, the negative voltage detection circuit determines that the negative voltage has the desired level. When the level of the output is lower than the desired level, the charge pump is stopped. Otherwise, a control signal is output to operate the charge pump so as to control the negative voltage at the desired level by the feed back control.
摘要翻译：负电压检测电路的检测电平与并入存储器件的MOS晶体管的阈值电压无关。负电压检测电路检测电荷泵的输出电压是否具有期望的电平，然后根据检测结果输出信号。负电压检测电路通过将负电压的倍数与正内参考电压Vref进行比较，将负电压进行比较，将 - （1 / n）（n为自然数）。当倍数和参考电压Vref彼此相等时，负电压检测电路确定负电压具有期望的电平。当输出电平低于所需电平时，电荷泵停止。否则，输出控制信号来操作电荷泵，以便通过反馈控制将负电压控制在期望的水平。

40. 发明授权

US5963500A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5963500A
公开(公告)日：1999-10-05
申请号：US30670
申请日：1998-02-25
申请人： Tadayuki Taura , Shigeru Atsumi , Hironori Banba
发明人： Tadayuki Taura , Shigeru Atsumi , Hironori Banba
IPC分类号： G11C16/06 , G11C8/10 , G11C29/04 , G11C29/12 , G11C29/24 , G11C29/50 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C8/00
CPC分类号： G11C29/50004 , G11C29/50 , G11C8/10 , G11C16/04
摘要： A decoder circuit selectively controls the transfer gate group. The transfer gate group is stacked so as to form a tree structure having multiple stages of transfer gates and enable a monitoring bus line to be connected to any column in a memory cell array. This configuration enables the current in each memory cell to be monitored at an external pad via a single bus line, which reduces the area occupied by the bus lines, suppressing an increase in the chip size.
摘要翻译：解码器电路选择性地控制传输门组。堆叠传输门组，以形成具有多级传输门的树形结构，并使监控总线能够连接到存储单元阵列中的任何列。该配置使得能够通过单个总线在每个存储单元中的外部焊盘处监视电流，这减少了总线占用的面积，从而抑制了芯片尺寸的增加。

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