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31. 发明申请

US20080261371A1 VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION 有权
标题翻译：具有主要载体累积层的垂直双极晶体管，作为用于SOI BiCMOS的半导体器件，具有减少的基底氧化物厚度用于低基板偏压运行
公开(公告)号：US20080261371A1
公开(公告)日：2008-10-23
申请号：US12144998
申请日：2008-06-24
申请人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
发明人： Herbert L. Ho , Mahender Kumar , Qiging Ouyang , Paul A. Papworth , Christopher D. Sheraw , Michael D. Steigerwalt
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66265
摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.
摘要翻译：本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。这种器件的优点是其类似CMOS的工艺。因此，可以简化集成方案，并且可以显着降低制造成本。本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。还提供了背栅CMOS装置。

32. 发明授权

US07439149B1 Structure and method for forming SOI trench memory with single-sided strap 失效
标题翻译：用单面带形成SOI沟槽存储器的结构和方法
公开(公告)号：US07439149B1
公开(公告)日：2008-10-21
申请号：US11861704
申请日：2007-09-26
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

33. 发明授权

US07394131B2 STI formation in semiconductor device including SOI and bulk silicon regions 有权
标题翻译：在包括SOI和体硅区域的半导体器件中形成STI
公开(公告)号：US07394131B2
公开(公告)日：2008-07-01
申请号：US11425467
申请日：2006-06-21
申请人： Michael D. Steigerwalt , Mahender Kumar , Herbert L. Ho , David M. Dobuzinsky , Johnathan E. Faltermeier , Denise Pendleton
发明人： Michael D. Steigerwalt , Mahender Kumar , Herbert L. Ho , David M. Dobuzinsky , Johnathan E. Faltermeier , Denise Pendleton
IPC分类号： H01L27/01
CPC分类号： H01L21/7624 , H01L21/3081 , H01L21/31612 , H01L21/76283
摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.
摘要翻译：公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻，并蚀刻穿过SOI区域的埋层绝缘体。用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

34. 发明授权

US07078756B2 Collarless trench DRAM device 失效
标题翻译：无领沟槽DRAM器件
公开(公告)号：US07078756B2
公开(公告)日：2006-07-18
申请号：US10904933
申请日：2004-12-06
申请人： Yoichi Otani , Herbert L. Ho , Babar A. Khan , Paul C. Parries
发明人： Yoichi Otani , Herbert L. Ho , Babar A. Khan , Paul C. Parries
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.
摘要翻译：本发明提供了具有最小的垂直寄生FET泄漏的无凹槽沟槽半导体存储器件及其形成方法。

35. 发明授权

US06964897B2 SOI trench capacitor cell incorporating a low-leakage floating body array transistor 有权
标题翻译：掺有低泄漏浮体阵列晶体管的SOI沟槽电容器单元
公开(公告)号：US06964897B2
公开(公告)日：2005-11-15
申请号：US10250157
申请日：2003-06-09
申请人： Karen A. Bard , David M. Dobuzinsky , Herbert L. Ho , Mahendar Kumar , Denise Pendleton , Michael D. Steigerwalt , Brian L. Walsh
发明人： Karen A. Bard , David M. Dobuzinsky , Herbert L. Ho , Mahendar Kumar , Denise Pendleton , Michael D. Steigerwalt , Brian L. Walsh
IPC分类号： H01L21/77 , H01L21/334 , H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/1203 , H01L29/7841
摘要： A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.
摘要翻译：在整个阵列中延伸的具有均匀BOX层的SOI晶片中的DRAM阵列消除了处理中的环氧化物步骤; 将掩埋板与植入物连接，该植入物又连接到延伸穿过设备层的导电插塞和被偏置在地面上的盒子; 而通过晶体管是具有浮动体的平面NFET，其具有通过接地位线接地的泄漏放电路径。

36. 发明授权

US06635525B1 Method of making backside buried strap for SOI DRAM trench capacitor 失效
标题翻译：制造SOI DRAM沟槽电容器的背面掩埋带的方法
公开(公告)号：US06635525B1
公开(公告)日：2003-10-21
申请号：US10161960
申请日：2002-06-03
申请人： Jack A. Mandelman , Herbert L. Ho
发明人： Jack A. Mandelman , Herbert L. Ho
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L21/84 , H01L27/10829 , H01L27/1203 , H01L29/66181
摘要： In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.
摘要翻译：在具有沟槽电容器DRAM阵列的SOI集成电路中，绝缘层的减小的厚度导致在沟槽电容器之间传播的通过字线之间的串扰。在沟槽顶部增加凹槽的深度并横向遮蔽绝缘层允许来自电容器中心电极的掩埋带与SOI层的背面接触，从而增加了通过字线和背带。

37. 发明授权

US06503798B1 Low resistance strap for high density trench DRAMS 失效
标题翻译：低电阻带用于高密度沟槽DRAMS
公开(公告)号：US06503798B1
公开(公告)日：2003-01-07
申请号：US09609168
申请日：2000-06-30
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Herbert L. Ho , Akira Sudo
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Herbert L. Ho , Akira Sudo
IPC分类号： H01L21336
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the strap comprises a plurality of strap conductors and the strap has a lower resistance than the conductor. The conductor comprises a first material having a first resistance and the strap comprises a second material different than the first material having a second resistance, wherein the second resistance is lower than the first resistance. The plurality of strap conductors comprises at least two electrically connected strap conductors, and a first strap conductor is adjacent the conductor and a second strap conductor is adjacent the transistor and the first strap conductor has an improved interface with the conductor. The strap comprises a lip strap, wherein the strap forms an L-shape. At least one of the plurality of the strap conductors is contiguous with a corner of the trench, and the plurality of strap conductors comprises a first strap conductor and a second strap conductor and the conductor is contiguous with the first strap conductor and the second strap conductor such that the second strap conductor and the conductor form an L-shape.
摘要翻译：一种用于动态随机存取装置的方法和结构，其包括具有沟槽的衬底，沟槽中的导体，与沟槽相邻的晶体管和电连接导体和晶体管的导电带，其中带包括多个带状导体并且带子具有比导体更低的电阻。导体包括具有第一电阻的第一材料，并且带包括不同于具有第二电阻的第一材料的第二材料，其中第二电阻低于第一电阻。多个带状导体包括至少两个电连接的带状导体，并且第一带导体与导体相邻，并且第二带导体与晶体管相邻，并且第一带导体具有与导体的改进的界面。带子包括唇带，其中带子形成L形。所述多个带状导体中的至少一个与所述沟槽的角部邻接，并且所述多个带状导体包括第一带状导体和第二带状导体，并且所述导体与所述第一带状导体和所述第二带状导体使得第二带状导体和导体形成L形。

38. 发明授权

US5356837A Method of making epitaxial cobalt silicide using a thin metal underlayer 失效
标题翻译：使用薄金属底层制造外延钴硅化物的方法
公开(公告)号：US5356837A
公开(公告)日：1994-10-18
申请号：US145429
申请日：1993-10-29
申请人： Peter J. Geiss , Thomas J. Licata , Herbert L. Ho , James G. Ryan
发明人： Peter J. Geiss , Thomas J. Licata , Herbert L. Ho , James G. Ryan
IPC分类号： H01L21/28 , C30B1/00 , H01L21/223 , H01L21/225 , H01L21/285 , H01L21/8238 , H01L27/092 , H01L21/44
CPC分类号： H01L21/28518 , C30B1/00 , C30B29/10 , H01L21/2257
摘要： An epitaxial cobalt silicide film is formed using a thin metal underlayer, which is placed underneath a cobalt layer prior to a heating step which forms the silicide film. More specifically, a refractory metal layer comprising tungsten, chromium, molybdenum, or a silicide thereof, is formed overlying a silicon substrate on a semiconductor wafer. A cobalt layer is formed overlying the refractory metal layer. Next, the wafer is annealed at a temperature sufficiently high to form an epitaxial cobalt silicide film overlying the silicon substrate. Following this annealing step, a cobalt-silicon-refractory metal alloy remains overlying the epitaxial cobalt silicide film. This silicide is then used to form a shallow P-N junction by dopant out-diffusion. First, either a P or N-type dopant is implanted into the silicide film so that substantially none of the dopant is implanted into the underlying silicon substrate. After implanting, the dopant is out-diffused from the silicide film into the underlying silicon substrate at a drive temperature sufficiently high to form the desired P-N junction.
摘要翻译：使用薄金属底层形成外延钴硅化物膜，该金属底层在形成硅化物膜的加热步骤之前放置在钴层下方。更具体地，在半导体晶片上的硅衬底上形成包含钨，铬，钼或其硅化物的难熔金属层。形成覆盖难熔金属层的钴层。接下来，将晶片在足够高的温度下退火以形成覆盖硅衬底的外延钴硅化物膜。在该退火步骤之后，钴 - 硅 - 难熔金属合金保留在外延钴硅化物膜上。然后将该硅化物用于通过掺杂剂外扩散形成浅P-N结。首先，将P或N型掺杂剂注入到硅化物膜中，使得基本上没有掺杂剂注入到下面的硅衬底中。在植入之后，掺杂剂在足够高的驱动温度下从硅化物薄膜扩散到下面的硅衬底中以形成所需的P-N结。

39. 发明授权

US08877603B2 Semiconductor-on-oxide structure and method of forming 有权
标题翻译：半导体氧化物结构及其形成方法
公开(公告)号：US08877603B2
公开(公告)日：2014-11-04
申请号：US13435056
申请日：2012-03-30
申请人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L21/76 , H01L21/30 , H01L21/46
CPC分类号： H01L29/06 , H01L21/76254
摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
摘要翻译：公开了形成这种结构的半导体 - 氧化物结构和相关方法。在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

40. 发明授权

US08753936B2 Changing effective work function using ion implantation during dual work function metal gate integration 有权
标题翻译：在双功能金属门集成中，使用离子注入来改变有效的功函数
公开(公告)号：US08753936B2
公开(公告)日：2014-06-17
申请号：US12190220
申请日：2008-08-12
申请人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8234
CPC分类号： H01L29/49 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/517
摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
摘要翻译：提出了离子注入来改变双功能金属栅极整合的有效功函数。一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

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