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31. 发明授权

US06503833B1 Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby 有权
标题翻译：自对准硅化物（硅化物）工艺，用于应变硅MOSFET on SiGe和由此形成的结构
公开(公告)号：US06503833B1
公开(公告)日：2003-01-07
申请号：US09712264
申请日：2000-11-15
申请人： Atul Champaklal Ajmera , Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin Kok Chan , Guy Moshe Cohen , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
发明人： Atul Champaklal Ajmera , Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin Kok Chan , Guy Moshe Cohen , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/1054 , H01L29/7834
摘要： A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.
摘要翻译：一种形成半导体衬底（及其结构）的方法，包括在栅极的各个侧面上设置硅化物半导体衬底，该半导体衬底包括形成在其中的源极和漏极，在栅极，源极和漏极区域上沉积金属膜，在第一预定温度下具有Si的金属膜，以形成金属 - 硅合金，蚀刻未反应的金属，在源极漏极和栅极区域上沉积硅膜，在第二预定温度下退火衬底以形成金属-Si2 合金，并选择性地蚀刻未反应的Si。

32. 发明授权

US07795677B2 Nanowire field-effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US07795677B2
公开(公告)日：2010-09-14
申请号：US11850608
申请日：2007-09-05
申请人： Sarunya Bangsaruntip , Guy Moshe Cohen , Katherine Lynn Saenger
发明人： Sarunya Bangsaruntip , Guy Moshe Cohen , Katherine Lynn Saenger
IPC分类号： H01L29/72
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/20 , H01L29/22 , H01L29/42392 , H01L29/458 , H01L29/66545 , H01L29/66628 , H01L29/78696 , Y10S977/762 , Y10S977/784 , Y10S977/938
摘要： Field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a FET is provided. The FET comprises a substrate having a silicon-on-insulator (SOI) layer which is divided into at least two sections electrically isolated from one another, one section included in a source region and the other section included in a drain region; a channel region connecting the source region and the drain region and including at least one nanowire; an epitaxial semiconductor material, grown from the SOI layer, covering the nanowire and attaching the nanowire to each section of the SOI layer; and a gate over the channel region.
摘要翻译：提供具有纳米线通道的场效应晶体管（FET）。一方面，提供了FET。 FET包括具有绝缘体上硅（SOI）层的衬底，其被划分成彼此电隔离的至少两个部分，一个部分包括在源极区域中，另一个部分包括在漏极区域中; 连接源极区域和漏极区域并且包括至少一个纳米线的沟道区域; 从SOI层生长的外延半导体材料，覆盖纳米线并将纳米线附接到SOI层的每个部分; 和通道区域上的门。

33. 发明申请

US20090061568A1 Techniques for Fabricating Nanowire Field-Effect Transistors 有权
标题翻译：制造纳米线场效应晶体管的技术
公开(公告)号：US20090061568A1
公开(公告)日：2009-03-05
申请号：US11850644
申请日：2007-09-05
申请人： Sarunya Bangsaruntip , Guy Moshe Cohen , Katherine Lynn Saenger
发明人： Sarunya Bangsaruntip , Guy Moshe Cohen , Katherine Lynn Saenger
IPC分类号： H01L21/84
CPC分类号： H01L29/66545 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： Techniques for the fabrication of field-effect transistors (FETs) having nanowire channels are provided. In one aspect, a method of fabricating a FET is provided comprising the following steps. A substrate is provided having a silicon-on-insulator (SOI) layer. At least one nanowire is deposited over the SOI layer. A sacrificial gate is formed over the SOI layer so as to cover a portion of the nanowire that forms a channel region. An epitaxial semiconductor material is selectively grown from the SOI layer that covers the nanowire and attaches the nanowire to the SOI layer in a source region and in a drain region. The sacrificial gate is removed. An oxide is formed that divides the SOI layer into at least two electrically isolated sections, one section included in the source region and the other section included in the drain region. A gate dielectric layer is formed over the channel region. A gate is formed over the channel region separated from the nanowire by the gate dielectric layer. A metal-semiconductor alloy is formed over the source and drain regions.
摘要翻译：提供了具有纳米线通道的场效应晶体管（FET）制造技术。一方面，提供一种制造FET的方法，包括以下步骤。提供了具有绝缘体上硅（SOI）层的衬底。在SOI层上沉积至少一个纳米线。牺牲栅极形成在SOI层上，以覆盖形成沟道区的纳米线的一部分。从覆盖纳米线的SOI层选择性地生长外延半导体材料，并将纳米线附着在源极区域和漏极区域中的SOI层。牺牲栅被去除。形成氧化物，其将SOI层分成至少两个电隔离部分，一个部分包括在源极区域中，另一个部分包括在漏极区域中。栅极电介质层形成在沟道区域上。栅极形成在通过栅极介电层与纳米线分离的沟道区上。在源极和漏极区域上形成金属 - 半导体合金。

34. 发明申请

US20080293246A1 VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT 失效
标题翻译：具有纳米通道和硅胶底座的垂直FET
公开(公告)号：US20080293246A1
公开(公告)日：2008-11-27
申请号：US12167686
申请日：2008-07-03
申请人： Guy Moshe Cohen , Paul M. Solomon
发明人： Guy Moshe Cohen , Paul M. Solomon
IPC分类号： H01L21/44
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/0237 , H01L21/02381 , H01L21/02433 , H01L21/02521 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02645 , H01L21/02653 , H01L29/045 , H01L29/0676 , H01L29/66666 , H01L29/7827 , H01L29/7828 , Y10S977/762 , Y10S977/938
摘要： A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.
摘要翻译：公开了一种具有形成FET沟道的纳米线的垂直FET结构。纳米线形成在导电硅化物层上。纳米线由周围的门浇口。顶部和底部绝缘体插塞用作栅极间隔，并减少栅极 - 源极和栅极 - 漏极电容。

35. 发明授权

US06972250B2 Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device 失效
标题翻译：通过垂直自对准CoSi2在升高的源极漏极Si / SiGe器件上形成的超低接触电阻CMOS的方法和结构
公开(公告)号：US06972250B2
公开(公告)日：2005-12-06
申请号：US10419888
申请日：2003-04-22
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8238 , H01L29/161 , H01L21/4763
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/161 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.
摘要翻译：形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中金属层具有第二预定厚度。然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗入下面的SiGe层。

36. 发明授权

US06716708B2 Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby 有权
标题翻译：自对准硅化物工艺利用离子植入物降低硅消耗，并控制硅化物形成温度和由此形成的结构
公开(公告)号：US06716708B2
公开(公告)日：2004-04-06
申请号：US10299688
申请日：2002-11-20
申请人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
发明人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L29/41783
摘要： A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译：一种用于在具有所述含硅区域的受控消耗的含硅区域上形成金属硅化物接触的方法（和所得结构）包括将Ge注入含硅区域中，在硅上形成覆盖的金属 - 硅混合物层在第一温度下使金属硅混合物与硅反应以形成金属硅合金，蚀刻金属 - 硅混合物层的未反应部分，在金属硅合金层上形成覆盖硅层，在第二温度下退火温度以形成金属-Si2的合金，并且选择性地蚀刻未反应的硅层。

37. 发明授权

US06667528B2 Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same 有权
标题翻译：具有反射镜和背面接触的绝缘体上半导体侧面p-i-n光电探测器及其形成方法
公开(公告)号：US06667528B2
公开(公告)日：2003-12-23
申请号：US10033902
申请日：2002-01-03
申请人： Guy Moshe Cohen , Kern Rim , Dennis L. Rogers , Jeremy Daniel Schaub , Min Yang
发明人： Guy Moshe Cohen , Kern Rim , Dennis L. Rogers , Jeremy Daniel Schaub , Min Yang
IPC分类号： H01L31058
CPC分类号： H01L31/105 , H01L31/03529 , H01L31/03921 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.
摘要翻译：光电检测器（及其制造方法）包括半导体衬底，形成在衬底上的埋入绝缘体，形成在埋层绝缘体上的掩埋反射镜，形成在导体上的绝缘体上半导体层（SOI）层，形成在绝缘体上半导体层中的p型和p型掺杂指，以及与p型掺杂指和n型掺杂指之一的背面接触。

38. 发明授权

US06645861B2 Self-aligned silicide process for silicon sidewall source and drain contacts 失效
标题翻译：用于硅侧壁源极和漏极触点的自对准硅化物工艺
公开(公告)号：US06645861B2
公开(公告)日：2003-11-11
申请号：US09836197
申请日：2001-04-18
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L2144
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译：在具有含硅区域的受控消耗的非平面含硅区域上形成金属硅化物接触的方法（以及由此形成的结构）包括在含硅区域上形成覆盖金属层，在金属上形成硅层层，相对于金属的硅层各向异性地选择性地蚀刻，在第一温度下使金属与硅反应以形成金属硅合金，蚀刻金属层的未反应部分，在第二温度退火以形成金属合金 -Si2，并且选择性地蚀刻未反应的硅层。

39. 发明授权

US06300218B1 Method for patterning a buried oxide thickness for a separation by implanted oxygen (simox) process 失效
标题翻译：通过注入氧（simox）工艺图案化用于分离的掩埋氧化物厚度的方法
公开(公告)号：US06300218B1
公开(公告)日：2001-10-09
申请号：US09567095
申请日：2000-05-08
申请人： Guy Moshe Cohen , Devendra Kumar Sadana
发明人： Guy Moshe Cohen , Devendra Kumar Sadana
IPC分类号： H01L2176
CPC分类号： H01L21/76243
摘要： A method of forming a patterned buried oxide film, includes performing an implantation into a substrate, forming a mask on at least portions of the substrate for controlling the implantation diffusion, and annealing the substrate to form a buried oxide. The mask may be selectively patterned. A region that is covered by the mask has a thinner buried oxide than an area which is exposed directly to the annealing ambient.
摘要翻译：形成图案化的掩埋氧化膜的方法包括：在衬底中进行注入，在用于控制注入扩散的衬底的至少部分上形成掩模，以及退火衬底以形成掩埋氧化物。掩模可以被选择性地图案化。由掩模覆盖的区域比直接暴露于退火环境的区域具有更薄的掩埋氧化物。

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