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31. 发明授权

US6144348A Plasma display panel having dedicated priming electrodes outside display area and driving method for same panel 失效
标题翻译：等离子显示面板具有专用的底漆电极在显示区域外面，同时驱动方法
公开(公告)号：US6144348A
公开(公告)日：2000-11-07
申请号：US906111
申请日：1997-08-05
申请人： Yoshikazu Kanazawa , Fumitaka Asami
发明人： Yoshikazu Kanazawa , Fumitaka Asami
IPC分类号： G09G3/288 , G09G3/291 , G09G3/292 , G09G3/293 , G09G3/298 , H01J11/12 , H01J11/14 , H01J11/22 , H01J11/24 , H01J11/26 , H01J11/28 , H01J11/34 , H01J11/36 , H01J11/38 , H01J11/44 , G09G3/28
CPC分类号： G09G3/296 , G09G3/2927 , G09G3/2932 , G09G2320/0228
摘要： A plasma display panel and driving method thereof perform addressing at a high speed and a low voltage without deteriorating contrast. Priming electrodes forming priming cells are located outside but adjacent a display area. Glow occurring in the priming cells is intercepted. When priming discharge is induced at a reset step, voltages lower than a discharge start voltage are applied to first (X) and second (Y) electrodes and third (address) electrodes respectively. Despite the voltages being lower than the discharge start voltage, once discharge is induced in the priming cells, discharge starts in adjoining cells. The discharge then spreads successively over all the cells, thus inducing discharge in all the cells. Consequently, wall charge is produced in all the cells.
摘要翻译：等离子体显示面板及其驱动方法以高速低电压进行寻址，而不会降低对比度。形成起始电池的起始电极位于显示区域外部但邻近显示区域。在引发细胞中发生的辉光被截获。当在复位步骤中引发起动放电时，分别向第一（X）和第二（Y）电极和第三（地址）电极施加低于放电开始电压的电压。尽管电压低于放电开始电压，一旦在引发电池中引发放电，则在邻接的电池中开始放电。然后放电遍及所有电池，从而在所有电池中引起放电。因此，在所有电池中产生壁电荷。

32. 发明授权

US5391904A Semiconductor delay circuit device 失效
标题翻译：半导体延迟电路器件
公开(公告)号：US5391904A
公开(公告)日：1995-02-21
申请号：US080651
申请日：1993-06-22
申请人： Fumitaka Asami , Shinya Udo
发明人： Fumitaka Asami , Shinya Udo
IPC分类号： H01L27/092 , H01L27/112 , H01L29/76 , H01L23/48 , H01L29/94 , H01L31/062
CPC分类号： H01L27/0925 , H01L27/112
摘要： A semiconductor delay circuit device comprises a pair of transistors of the same conduction type having source regions that are arranged adjacent to each other and facing each other, and a substrate contact diffusion region whose conduction type is opposite to that of the source regions. The substrate contact diffusion region extends between the source regions. Therefore, the source regions of the transistors do not influence each other.
摘要翻译：半导体延迟电路器件包括具有彼此相邻布置并且彼此相对的源极区的相同导电类型的一对晶体管，以及导电类型与源极区相反的衬底接触扩散区域。衬底接触扩散区域在源极区域之间延伸。因此，晶体管的源极区域不会相互影响。

33. 发明授权

US4786823A Noise pulse suppressing circuit in digital system 失效
标题翻译：数字系统中的噪声脉冲抑制电路
公开(公告)号：US4786823A
公开(公告)日：1988-11-22
申请号：US39337
申请日：1987-04-17
申请人： Masato Abe , Fumitaka Asami
发明人： Masato Abe , Fumitaka Asami
IPC分类号： H03H17/00 , H03K3/13 , H03K5/1252 , H03K5/22
CPC分类号： H03K5/1252
摘要： Noise pulses having both polarities which are superposed on an input signal having a binary state of H/L levels forming a rectangular waveform, are suppressed or eliminated before transferring the input signal to an output stage. A noise pulse suppressing circuit is provided which comprises a latch circuit, a counter circuit, and a logic circuit including NAND gates and INVERTERs. For the latch circuit and the counter circuit, D-type flip-flops are also utilized. The input signal is inputted to a data input terminal of a flip-flop of the latch circuit and outputted from the data output terminal thereof. The latch circuits are triggered by a pulse signal applied to a clock terminal thereof. The above triggering pulse signal is generated by the counter circuit and the logic circuit, and it has a short pulse waveform responding to the input signal but delayed. No pulse in the output is produced which corresponds to the noise pulses in the input signal.
摘要翻译：在将输入信号传送到输出级之前，抑制或消除具有叠加在形成矩形波形的H / L电平的二进制状态的输入信号上的两个极性的噪声脉冲。提供一种噪声脉冲抑制电路，其包括锁存电路，计数器电路和包括与非门和反相器的逻辑电路。对于锁存电路和计数器电路，也使用D型触发器。输入信号被输入到锁存电路的触发器的数据输入端，并从其数据输出端输出。锁存电路由施加到其时钟端的脉冲信号触发。上述触发脉冲信号由计数器电路和逻辑电路产生，并且具有响应输入信号但延迟的短脉冲波形。不产生与输入信号中的噪声脉冲相对应的输出脉冲。

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