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31. 发明申请

US20100232216A1 Phase-Change Memory Device 有权
标题翻译：相变存储器件
公开(公告)号：US20100232216A1
公开(公告)日：2010-09-16
申请号：US12488637
申请日：2009-06-22
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/10 , G11C8/14 , G11C13/0004
摘要： A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of cell matrixes and includes word line decoding units that are each shared by a plurality of cell matrixes arranged in a row direction and are configured to activate one of global row signals according to a first row address, local row switch units that are provided to the respective cell matrixes and are configured to connect local current lines to corresponding word lines in response to the activated global row signal, bus connecting units that are provided to the respective cell matrixes and are configured to connect the local current lines to global current lines, and enabling units configured to activate one of the global current lines according to a second row address.
摘要翻译：相变存储器件能够通过改善对写入/读取操作选择存储单元的处理来降低电流消耗并防止由于线路负载引起的性能劣化。相变存储器件具有多个单元矩阵，并且包括字线解码单元，每个字线解码单元由行行方向排列的多个单元矩阵共享，并且被配置为根据第一行地址激活全局行信号之一，本地行开关单元，其被提供给相应的单元矩阵，并且被配置为响应于激活的全局行信号将局部当前行连接到对应的字线，提供给相应单元矩阵的总线连接单元被配置为将局部当前线路到全局当前线路，以及启用被配置为根据第二行地址激活全局当前线路之一的单元。

32. 发明申请

US20100147799A1 CHEMICAL MECHANICAL POLISHING METHOD 有权
标题翻译：化学机械抛光方法
公开(公告)号：US20100147799A1
公开(公告)日：2010-06-17
申请号：US12711344
申请日：2010-02-24
申请人： Dong-Keun Kim , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Dong-Keun Kim , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： C23F1/00
CPC分类号： H01L21/76819 , C09G1/02 , H01L21/31053
摘要： In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.
摘要翻译：在一个实施方案中，一种用于具有第一层和阶梯部分的基材的化学机械抛光方法。第一层的表面位于台阶部的上表面的上方。通过使用具有自停特性的第一浆料组合物在第一层上进行用于选择性去除台阶部分的抛光工艺，使得第一层变成具有基本平坦表面的第二层。使用不具有自停特性的第二浆料组合物进行第二抛光处理，直到阶梯部分的上表面露出。

33. 发明授权

US07554876B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07554876B2
公开(公告)日：2009-06-30
申请号：US11819565
申请日：2007-06-28
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/06
摘要： A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving circuits for driving N word lines of a cell block, the N unit driving circuits being divided into M group driving circuits; a common address latch unit for latching a first address for selecting one of the M group driving circuits of the word line driver unit, and outputting the latched first address to the word line driver unit; and an address latch unit for latching a second address for selecting a unit driving circuit of the selected group driving circuit in the word line driver unit, and outputting a latched second address to the word line driver unit.
摘要翻译：半导体存储器件可以有效地选择字线。半导体存储器件包括字线驱动器单元，用于包括用于驱动单元块的N个字线的N个单位驱动电路，N个单元驱动电路被分成M组驱动电路; 公共地址锁存单元，用于锁存用于选择字线驱动器单元的M组驱动电路中的一个的第一地址，并将锁存的第一地址输出到字线驱动器单元; 以及地址锁存单元，用于锁存用于在字线驱动器单元中选择所选择的组驱动电路的单元驱动电路的第二地址，并将锁存的第二地址输出到字线驱动器单元。

34. 发明授权

US07539073B2 Memory device with auxiliary precharge unit to improve precharge operation for bit line circuitry 有权
标题翻译：具有辅助预充电单元的存储器件，用于改善位线电路的预充电操作
公开(公告)号：US07539073B2
公开(公告)日：2009-05-26
申请号：US10877880
申请日：2004-06-25
申请人： Dong-Keun Kim , Chang-Ho Do
发明人： Dong-Keun Kim , Chang-Ho Do
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12
摘要： A semiconductor memory device having a shared bit line sense amplifier structure is provided. The semiconductor memory device includes: a plurality of cell arrays each of which has a plurality of bit line pairs, in which the cell arrays includes a first cell array disposed at an edge portion of a cell region and a second cell array disposed adjacent to the first cell array; a first precharging unit for precharging some bit line pairs of the first or second cell array; a second precharging unit for precharging the other bit line pairs of the first cell array; and an auxiliary precharging unit for assisting a precharge operation of the second precharging unit.
摘要翻译：提供具有共享位线读出放大器结构的半导体存储器件。半导体存储器件包括：多个单元阵列，每个单元阵列具有多个位线对，其中单元阵列包括设置在单元区域的边缘部分处的第一单元阵列和邻近单元阵列设置的第二单元阵列第一个单元格阵列; 用于对所述第一或第二单元阵列的某些位线对进行预充电的第一预充电单元; 第二预充电单元，用于对第一单元阵列的其它位线对进行预充电; 以及用于辅助第二预充电单元的预充电操作的辅助预充电单元。

35. 发明授权

US07535777B2 Driving signal generator for bit line sense amplifier driver 有权
标题翻译：用于位线读出放大器驱动的驱动信号发生器
公开(公告)号：US07535777B2
公开(公告)日：2009-05-19
申请号：US11529283
申请日：2006-09-29
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C7/08 , G11C7/22
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065 , G11C11/4074 , G11C2207/065
摘要： A semiconductor memory device includes an over driver for driving a pull-up power line of a bit line sense amplifier by an over driving signal, a normal driver for driving the pull-up power line of the bit line sense amplifier by a normal driving signal, and a driving signal generating circuit, in response to a write signal, for generating a driving signal to drive the over driver for a predetermined interval and thereafter to drive the normal driver.
摘要翻译：半导体存储器件包括用于通过过驱动信号驱动位线读出放大器的上拉电源线的过驱动器，用于通过正常驱动信号驱动位线读出放大器的上拉电源线的正常驱动器以及驱动信号发生电路，响应于写入信号，用于产生用于驱动过驱动器一段预定间隔的驱动信号，然后驱动正常驱动器。

36. 发明申请

US20070070711A1 Driving signal generator for bit line sense amplifier driver 有权
标题翻译：用于位线读出放大器驱动的驱动信号发生器
公开(公告)号：US20070070711A1
公开(公告)日：2007-03-29
申请号：US11529283
申请日：2006-09-29
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C7/10
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065 , G11C11/4074 , G11C2207/065
摘要： A semiconductor memory device includes an over driver for driving a pull-up power line of a bit line sense amplifier by an over driving signal, a normal driver for driving the pull-up power line of the bit line sense amplifier by a normal driving signal, and a driving signal generating circuit, in response to a write signal, for generating a driving signal to drive the over driver for a predetermined interval and thereafter to drive the normal driver.
摘要翻译：半导体存储器件包括用于通过过驱动信号驱动位线读出放大器的上拉电源线的过驱动器，用于通过正常驱动信号驱动位线读出放大器的上拉电源线的正常驱动器以及驱动信号发生电路，响应于写入信号，用于产生用于驱动过驱动器一段预定间隔的驱动信号，然后驱动正常驱动器。

37. 发明授权

US07139211B2 Semiconductor memory device for reducing cell area 有权
公开(公告)号：US07139211B2
公开(公告)日：2006-11-21
申请号：US11017683
申请日：2004-12-22
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.

38. 发明授权

US5776993A Thermoplastic PVC foam composition 失效
标题翻译：热塑性PVC泡沫组合物
公开(公告)号：US5776993A
公开(公告)日：1998-07-07
申请号：US697948
申请日：1996-09-03
申请人： Bong Sub Shin , Jae Yeon Lee , Dong Keun Kim , Seoun Jun Kim , Sung Ok Cho
发明人： Bong Sub Shin , Jae Yeon Lee , Dong Keun Kim , Seoun Jun Kim , Sung Ok Cho
IPC分类号： C08K5/00 , C08J9/00 , C08L7/00 , C08L9/00 , C08L19/00 , C08L21/00 , C08L23/08 , C08L27/06 , C08L31/04 , C08L51/00 , C08L51/04 , C08L75/00 , C08L75/04
CPC分类号： C08J9/0061 , C08J2327/06 , C08J2421/00
摘要： This invention relates to a thermoplastic PVC foam composition and more particularly, to the thermoplastic PVC foam composition suitable for a shoe material, which is characterized by the following fabrication and advantages. Some plasticizer and additive are added to the PVC base, plasticized by dioctyl phthalate (hereinafter called as "DOP") or epoxide soybean oil (hereinafter called as "ESO") to obtain the thermoplastic PVC foam composition. Then, one type of compound, selected from rubber thermoplastic urethane compound (hereinafter called as "TPU") and ethylenevinyl acetate copolymer (hereinafter called as "EVA"), was added to the mixture for modification. The desired product, so formed, has recognized some advantages in that a) possible foaming by extruder and injector including heating press, b) the composition, so foamed, can be regenerated, c) the desired product is light due to its low specific gravity, and d) physical property, anti-slip, abrasion-resistance and adhesiveness with other materials are remarkable.
摘要翻译：本发明涉及热塑性PVC泡沫组合物，更具体地说，涉及适用于鞋材的热塑性PVC泡沫组合物，其特征在于以下制造和优点。将一些增塑剂和添加剂加入到PVC基质中，由邻苯二甲酸二辛酯（以下称为“DOP”）或环氧化物大豆油（以下称为“ESO”）增塑，得到热塑性PVC泡沫组合物。然后，向混合物中加入一种选自橡胶热塑性氨基甲酸酯化合物（以下称为“TPU”）和乙烯 - 乙酸乙烯酯共聚物（以下称为“EVA”）的化合物进行改性。所形成的所需产品已经认识到一些优点，即a）通过挤出机和喷射器可能的发泡，包括加热压机，b）可以再生发泡的组合物，c）由于其比重低，所需产品是轻质的，d）物理性能，防滑，耐磨性和与其他材料的粘合性显着。

39. 发明授权

US09001559B2 Resistance change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US09001559B2
公开(公告)日：2015-04-07
申请号：US14018242
申请日：2013-09-04
申请人： Masahiro Takahashi , Akira Katayama , Dong Keun Kim , Byoung Chan Oh
发明人： Masahiro Takahashi , Akira Katayama , Dong Keun Kim , Byoung Chan Oh
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元，读出放大器和全局位线。存储单元设置在局部位线和字线相交的位置。存储单元连接到本地位线和字线。读出放大器通过向存储单元提供读取电流来读取存储在存储单元上的数据。全局位线连接在本地位线和读出放大器之间。全局位线将由读出放大器提供的读取电流馈送到本地位线。在本地位线和全局位线彼此连接之前，读出放大器对全局位线进行充电。

40. 发明申请

US20150084675A1 METHODS OF CONTROLLING CLOCKS IN SYSTEM ON CHIP INCLUDING FUNCTION BLOCKS, SYSTEMS ON CHIPS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 审中-公开
标题翻译：在包括功能块的芯片中控制时钟的方法，包括其中的芯片和半导体系统的系统的方法
公开(公告)号：US20150084675A1
公开(公告)日：2015-03-26
申请号：US14559131
申请日：2014-12-03
申请人： Dong Keun KIM , Sun Cheol KWON , Si Young KIM , Jae Gon LEE , Jung Hun HEO
发明人： Dong Keun KIM , Sun Cheol KWON , Si Young KIM , Jae Gon LEE , Jung Hun HEO
IPC分类号： H03K5/04
CPC分类号： H03K5/04 , G06F1/08 , G06F1/324 , H03K19/0016 , H03K21/00 , H03K21/10 , Y02D10/126 , Y02D50/20
摘要： A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.
摘要翻译：片上系统包括时钟控制器，其被配置为基于至少一个功能块的操作状态从活动状态到空闲状态的改变来减小至少一个功能块的操作频率。在包括至少一个功能块的操作片上系统的方法中，至少一个功能块的工作频率基于至少一个功能块从激活状态的操作状态的改变而减小到空闲状态。工作频率降低大于零。

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