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31. 发明授权

US07456468B2 Semiconductor device including high-k insulating layer and method of manufacturing the same 有权
标题翻译：包括高k绝缘层的半导体器件及其制造方法
公开(公告)号：US07456468B2
公开(公告)日：2008-11-25
申请号：US11335431
申请日：2006-01-18
申请人： Sang-Hun Jeon , Sung-Kyu Choi , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Ho Park , Jeong-Hee Han , Sang-Moo Choi
发明人： Sang-Hun Jeon , Sung-Kyu Choi , Chung-Woo Kim , Hyun-Sang Hwang , Sung-Ho Park , Jeong-Hee Han , Sang-Moo Choi
IPC分类号： H01L29/792
CPC分类号： H01L21/02148 , H01L21/02156 , H01L21/02159 , H01L21/28282 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/792
摘要： A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.
摘要翻译：半导体存储器件，第一掺杂剂区域和第二掺杂剂区域，设置在半导体衬底中的第一掺杂区域和第二掺杂剂区域，与第一掺杂区域和第二掺杂剂区域接触设置的绝缘层，绝缘层包括选自Hf，Zr，Y和Ln的材料以及设置在绝缘层上的栅电极层。

32. 发明申请

US20080128757A1 Non-volatile memory devices including vertical channels, methods of operating, and methods of fabricating the same 有权
标题翻译：包括垂直通道的非易失性存储器件，操作方法及其制造方法
公开(公告)号：US20080128757A1
公开(公告)日：2008-06-05
申请号：US11999135
申请日：2007-12-04
申请人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
发明人： Soo-Doo Chae , Chung-Woo Kim , Chan-Jin Park , Jeong-Hee Han , Byung-Gook Park , Il-Han Park
IPC分类号： G11C11/407 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0416 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A flash memory device can include a semiconductor pin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor pin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor pin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.
摘要翻译：闪速存储器件可以包括从第一导电类型的半导体衬底突出以在一个方向上延伸的半导体引脚，分别设置到半导体引脚的上部和下部的第一掺杂层和第二掺杂层，彼此垂直间隔开，第一和第二掺杂层具有第二导电类型，并且多个字线在半导体引脚的顶部和侧壁上延伸以与该方向相交。字线与第一掺杂层和第二掺杂层重叠以具有垂直沟道。

33. 发明授权

US07349262B2 Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices 有权
标题翻译：氧化硅氧化物半导体（SONOS）存储器件的编程方法
公开(公告)号：US07349262B2
公开(公告)日：2008-03-25
申请号：US11432375
申请日：2006-05-12
申请人： Youn-seok Jeong , Chung-woo Kim , Hee-soon Chae , Ju-hyung Kim , Jeong-hee Han , Jae-woong Hyun
发明人： Youn-seok Jeong , Chung-woo Kim , Hee-soon Chae , Ju-hyung Kim , Jeong-hee Han , Jae-woong Hyun
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.
摘要翻译：提供了一种编程氧化硅氮氧化物半导体（SONOS）存储器件的方法。 SONOS存储器件包括衬底，在衬底上间隔开的第一和第二杂质区，在第一和第二杂质区之间的衬底上形成的栅氧化层，在栅极氧化物层上形成的阱层，形成在绝缘层上的绝缘层陷阱层和形成在绝缘层上的栅电极。对SONOS设备进行编程的方法包括：通过向第一杂质区施加第一电压，向栅电极施加第一电压，向第二杂质区施加第二电压，将数据写入SONOS存储器件，其中第二电压为负电压。

34. 发明申请

US20070296026A1 SONOS memory device 审中-公开
标题翻译： SONOS存储设备
公开(公告)号：US20070296026A1
公开(公告)日：2007-12-27
申请号：US11896698
申请日：2007-09-05
申请人： Sang-hun Jeon , Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim
发明人： Sang-hun Jeon , Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/40117
摘要： A SONOS memory device, and a method of manufacturing the same, includes a substrate and a multifunctional device formed on the substrate. The multifunctional device performs both switching and data storing functions. The multifunctional device includes first and second impurities areas, a channel formed between the first and second impurities areas, and a stacked material formed on the channel for data storage. The stacked material for data storage is formed by sequentially stacking a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer.
摘要翻译： SONOS存储器件及其制造方法包括形成在衬底上的衬底和多功能器件。多功能设备执行切换和数据存储功能。多功能装置包括第一和第二杂质区域，形成在第一和第二杂质区域之间的通道，以及形成在通道上用于数据存储的堆叠材料。用于数据存储的层叠材料通过依次层叠隧道氧化物层，存储数据的存储节点层，阻挡层和电极层而形成。

35. 发明授权

US07187030B2 SONOS memory device 有权
标题翻译： SONOS存储设备
公开(公告)号：US07187030B2
公开(公告)日：2007-03-06
申请号：US10867706
申请日：2004-06-16
申请人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466
摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。可以在栅电极和捕获膜之间设置阻挡膜。第二标志的电荷载体可能是热孔。这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

36. 发明申请

US20060291286A1 Methods of programming silicon oxide nitride oxide semiconductor (SONOS) memory devices 有权
标题翻译：氧化硅氧化物半导体（SONOS）存储器件的编程方法
公开(公告)号：US20060291286A1
公开(公告)日：2006-12-28
申请号：US11432375
申请日：2006-05-12
申请人： Youn-seok Jeong , Chung-woo Kim , Hee-soon Chae , Ju-hyung Kim , Jeong-hee Han , Jae-woong Hyun
发明人： Youn-seok Jeong , Chung-woo Kim , Hee-soon Chae , Ju-hyung Kim , Jeong-hee Han , Jae-woong Hyun
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.
摘要翻译：提供了一种编程氧化硅氮氧化物半导体（SONOS）存储器件的方法。 SONOS存储器件包括衬底，在衬底上间隔开的第一和第二杂质区，在第一和第二杂质区之间的衬底上形成的栅氧化层，在栅极氧化物层上形成的阱层，形成在绝缘层上的绝缘层陷阱层和形成在绝缘层上的栅电极。对SONOS设备进行编程的方法包括：通过向第一杂质区施加第一电压，向栅电极施加第一电压，向第二杂质区施加第二电压，将数据写入SONOS存储器件，其中第二电压为负电压。

37. 发明申请

US20060255368A1 Single electron transistor having memory function and method of manufacturing the same 有权
标题翻译：具有记忆功能的单电子晶体管及其制造方法
公开(公告)号：US20060255368A1
公开(公告)日：2006-11-16
申请号：US11491281
申请日：2006-07-24
申请人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , H01L29/7888 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.
摘要翻译：公开了具有记忆功能的单电子晶体管及其制造方法。在单电子晶体管中，第一衬底和绝缘膜依次层叠，第二衬底层叠在绝缘膜上，并且包括源极区域，沟道区域和漏极区域，在第二衬底上形成隧穿膜在隧道膜上形成至少两个陷阱层，并且以间隔隔开，使得至少一个量子点可以在沟道区域中以相同的间隔形成，并且形成栅电极以接触至少两个陷阱层和至少两个陷阱层之间的隧道膜。由于单电子晶体管简单并且包括单个栅极电极，所以可以简化制造工艺及其操作电路，并且可以降低功耗。

38. 发明授权

US07105874B2 Single electron transistor having memory function 有权
标题翻译：具有记忆功能的单电子晶体管
公开(公告)号：US07105874B2
公开(公告)日：2006-09-12
申请号：US10773288
申请日：2004-02-09
申请人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Ju-hyung Kim
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , H01L29/7888 , Y10S977/937 , Y10S977/938
摘要： A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.
摘要翻译：公开了具有记忆功能的单电子晶体管及其制造方法。在单电子晶体管中，第一衬底和绝缘膜依次层叠，第二衬底层叠在绝缘膜上，并且包括源极区域，沟道区域和漏极区域，在第二衬底上形成隧穿膜在隧道膜上形成至少两个陷阱层，并且以间隔隔开，使得至少一个量子点可以在沟道区域中以相同的间隔形成，并且形成栅电极以接触至少两个陷阱层和至少两个陷阱层之间的隧道膜。由于单电子晶体管简单并且包括单个栅极电极，所以可以简化制造工艺及其操作电路，并且可以降低功耗。

39. 发明申请

US20060131636A1 Non-volatile memory device having improved erase efficiency and method of manufacturing the same 审中-公开
标题翻译：具有改善的擦除效率的非易失性存储器件及其制造方法
公开(公告)号：US20060131636A1
公开(公告)日：2006-06-22
申请号：US11249396
申请日：2005-10-14
申请人： Sang-hun Jeon , Chung-woo Kim
发明人： Sang-hun Jeon , Chung-woo Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment of the gate using an oxygen or CF4 plasma or ion implantation to increase a work function of an element forming the gate. Since the work function of the metal layer forming the gate can be further increased, an electron back tunneling can be suppressed during an erase operation.
摘要翻译：提供了具有改进的擦除效率的非易失性存储器件及其制造方法。该方法包括：在半导体衬底上形成隧道介电层，电荷俘获层，电荷阻挡层和栅极的堆叠结构; 以及使用氧或CF 4等离子体或离子注入来执行栅极的后处理以增加形成栅极的元件的功函数。由于可以进一步增加形成栅极的金属层的功函数，所以可以在擦除操作期间抑制电子反向隧穿。

40. 发明申请

US20060105524A1 Non-volatile device manufactured using ion-implantation and method of manufacture the same 审中-公开
标题翻译：使用离子注入制造的非易失性装置及其制造方法
公开(公告)号：US20060105524A1
公开(公告)日：2006-05-18
申请号：US11190827
申请日：2005-07-28
申请人： Jeong-hee Han , Hoon-young Cho , Chung-woo Kim , Chan-jin Park , Jong-soo Oh , Ki-hyun Cho
发明人： Jeong-hee Han , Hoon-young Cho , Chung-woo Kim , Chan-jin Park , Jong-soo Oh , Ki-hyun Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/31155 , B82Y10/00 , G11C16/0466 , H01L29/40114 , H01L29/40117 , H01L29/42332 , H01L29/7881
摘要： Embodiments of the invention include a non-volatile memory device manufactured using ion-implantation, and a method of manufacturing the same. A dielectric layer may be formed on a semiconductor substrate, and an ion implantation layer, which may be used as a charge trapping site, may be formed by ion implantation with Si or Ge. Then, an annealing process may be performed. Subsequently, a process for forming a transistor on the dielectric layer may be performed.
摘要翻译：本发明的实施例包括使用离子注入制造的非易失性存储器件及其制造方法。可以在半导体衬底上形成电介质层，并且可以通过用Si或Ge的离子注入形成可用作电荷捕获位点的离子注入层。然后，可以进行退火处理。随后，可以进行在电介质层上形成晶体管的工艺。

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