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31. 发明授权

US08140293B2 On die thermal sensor 有权
标题翻译：模具热传感器
公开(公告)号：US08140293B2
公开(公告)日：2012-03-20
申请号：US11819810
申请日：2007-06-29
申请人： Chun-Seok Jeong , Kee-Teok Park
发明人： Chun-Seok Jeong , Kee-Teok Park
IPC分类号： G01K7/00 , G01R31/00
CPC分类号： G01K7/425 , G11C7/04 , G11C11/406 , G11C11/40626
摘要： An on die thermal sensor (ODTS) for use in a semiconductor device includes a temperature information output unit for measuring an internal temperature of the semiconductor device to generate a temperature information code having temperature information, and updating the temperature information code according to a refresh period.
摘要翻译：用于半导体器件的裸片热传感器（ODTS）包括温度信息输出单元，用于测量半导体器件的内部温度以产生具有温度信息的温度信息代码，并根据刷新周期更新温度信息代码。

32. 发明授权

US08072822B2 Data alignment circuit and method of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的数据对准电路及方法
公开(公告)号：US08072822B2
公开(公告)日：2011-12-06
申请号：US12649066
申请日：2009-12-29
申请人： Chun Seok Jeong , Kee Teok Park , Chang Sik Yoo , Jang Woo Lee , Hong Jung Kim
发明人： Chun Seok Jeong , Kee Teok Park , Chang Sik Yoo , Jang Woo Lee , Hong Jung Kim
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222
摘要： A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.
摘要翻译：半导体存储装置的数据对准电路包括：数据选通时钟相位控制块，被配置为响应于选通延迟码来控制数据选通时钟信号的相位，并产生延迟的选通时钟信号; 多个数据相位控制块，被配置为响应于数据延迟码来控制输入数据的相位并产生延迟的数据; 多个数据对准块被配置为响应延迟的选通时钟信号来锁存延迟的数据，并产生锁存的数据和对准的数据; 以及延迟码生成块，被配置为执行确定所述锁存数据的相位的操作，并生成所述选通延迟码和所述数据延迟码。

33. 发明申请

US20110169552A1 ON DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH, INTEGRATED CIRCUIT WITH THE SAME AND METHOD FOR ON DIE THERMAL SENSOR SUITABLE FOR AUTO SELF REFRESH 有权
标题翻译：适用于自动自复印机的集成电路传感器，适用于自动自刷新的DIE热传感器的集成电路
公开(公告)号：US20110169552A1
公开(公告)日：2011-07-14
申请号：US13069175
申请日：2011-03-22
申请人： Chun-Seok JEONG
发明人： Chun-Seok JEONG
IPC分类号： H01L35/00
CPC分类号： G11C11/406 , G01K3/005 , G01K7/01 , G11C7/04 , G11C11/40615 , G11C11/40626
摘要： A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit.
摘要翻译：半导体存储器件包括：参考电压发生器，用于响应于自刷新使能控制信号产生各自具有不同电压电平的多个参考电压;以及电压比较器，用于通过比较每个参考电压产生控制自刷新操作周期的结果信号具有表示集成电路的内部温度的温度信息电压的多个参考电压。

34. 发明授权

US07936616B2 Die thermal sensor suitable for auto self refresh, integrated circuit with the same and method for on die thermal sensor suitable for auto self refresh 有权
标题翻译：适用于自动自刷新的模具热敏传感器，具有相同的集成电路和适用于自动自刷新的热敏传感器的方法
公开(公告)号：US07936616B2
公开(公告)日：2011-05-03
申请号：US12336202
申请日：2008-12-16
申请人： Chun-Seok Jeong
发明人： Chun-Seok Jeong
IPC分类号： G11C5/14
CPC分类号： G11C11/406 , G01K3/005 , G01K7/01 , G11C7/04 , G11C11/40615 , G11C11/40626
摘要： A semiconductor memory device includes a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit.
摘要翻译：半导体存储器件包括：参考电压发生器，用于响应于自刷新使能控制信号产生各自具有不同电压电平的多个参考电压;以及电压比较器，用于通过比较每个参考电压产生控制自刷新操作周期的结果信号具有表示集成电路的内部温度的温度信息电压的多个参考电压。

35. 发明授权

US07884637B2 Calibration circuit and semiconductor memory device with the same 有权
标题翻译：校准电路和半导体存储器件相同
公开(公告)号：US07884637B2
公开(公告)日：2011-02-08
申请号：US11967720
申请日：2007-12-31
申请人： Chun-Seok Jeong
发明人： Chun-Seok Jeong
IPC分类号： H03K17/16
CPC分类号： G11C7/1051 , G11C7/1057 , G11C17/18 , G11C2207/2254
摘要： A calibration circuit is capable of correcting an error of a calibration operation by adjusting a calibration code generated thereby. The calibration circuit of a semiconductor memory device includes a code generator, a calibration resistor unit, and a variable resistor unit. The code generator is configured to generate a calibration code for determining a termination resistance in response to a voltage of a first node and a reference voltage. The calibration resistor unit, which has internal resistors turned on/off in response to the calibration code, is connected to the first node. The variable resistor unit is connected in parallel with the calibration resistor unit and has a resistance that varies with a setting value.
摘要翻译：校准电路能够通过调整由此生成的校准代码来校正校准操作的误差。半导体存储器件的校准电路包括代码发生器，校准电阻器单元和可变电阻器单元。代码生成器被配置为生成用于响应于第一节点的电压和参考电压来确定终止电阻的校准代码。具有响应校准代码打开/关闭内部电阻的校准电阻器单元连接到第一节点。可变电阻单元与校准电阻单元并联连接，并具有随设定值而变化的电阻。

36. 发明授权

US07755383B2 Calibration circuit, semiconductor memory device including the same, and operating method of the calibration circuit 有权
标题翻译：校准电路，包括相同的半导体存储器件以及校准电路的操作方法
公开(公告)号：US07755383B2
公开(公告)日：2010-07-13
申请号：US12165110
申请日：2008-06-30
申请人： Chun-Seok Jeong , Seok-Cheol Yoon
发明人： Chun-Seok Jeong , Seok-Cheol Yoon
IPC分类号： H03K19/003
CPC分类号： H03K19/0016 , G11C7/1051 , G11C7/1057 , G11C2207/2254 , H03K19/0005
摘要： Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit configured to count a clock and allow the calibration unit to be enabled during a predetermined clock and a clock control unit configured to selectively supply the clock to the calibration control unit according to an operation mode of a semiconductor device employing the calibration circuit.
摘要翻译：校准电路，包括其的半导体存储器件和校准电路的操作方法包括：校准单元，被配置为生成用于控制终端电阻值的校准代码;校准控制单元，被配置为对时钟进行计数，并允许校准单元为在预定时钟期间使能;以及时钟控制单元，被配置为根据采用校准电路的半导体器件的操作模式，有选择地将时钟提供给校准控制单元。

37. 发明授权

US07692418B2 Band gap reference circuit and temperature information output apparatus using the same 有权
标题翻译：带隙基准电路和温度信息输出装置
公开(公告)号：US07692418B2
公开(公告)日：2010-04-06
申请号：US11647485
申请日：2006-12-29
申请人： Chun-Seok Jeong
发明人： Chun-Seok Jeong
IPC分类号： G05F3/16
CPC分类号： G05F3/30 , Y10S323/907
摘要： A BGR circuit includes a temperature-proportional current generating part configured to generate a current in proportion to a change in temperature through a plurality of current paths; a temperature-inverse proportional current generating part generates a current in inverse proportion to a change in temperature through a plurality of current paths. An internal voltage reference voltage generating part generates a reference voltage for an internal voltage using the current of the temperature-proportional current generating part and the current of the temperature-inverse proportional current generating part. A temperature voltage output part outputs a voltage corresponding to a change in temperature.
摘要翻译： BGR电路包括温度成比例的电流产生部件，被配置为通过多个电流通路产生与温度变化成比例的电流; 温度 - 反比例电流产生部分通过多个电流路径产生与温度变化成反比的电流。内部参考电压产生部分使用温度比例电流产生部分的电流和温度 - 反比例电流产生部分的电流产生用于内部电压的参考电压。温度电压输出部输出与温度变化对应的电压。

38. 发明授权

US07663962B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07663962B2
公开(公告)日：2010-02-16
申请号：US11824014
申请日：2007-06-29
申请人： Chun-Seok Jeong , Kang-Seol Lee
发明人： Chun-Seok Jeong , Kang-Seol Lee
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C7/1048 , G11C7/18 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device includes a bank, a data transfer line, a precharge control circuit, and a precharge line. The bank includes a multiplicity of cell mats arranged in a matrix form. Each of the cell mats has a plurality of unit cells. The data transfer line arranged between the cell mats transfers a data signal outputted from a selected cell mat among the cell mats. The precharge control circuit disposed on the edge of the bank controls the precharge of the data transfer line. The precharge line arranged between first and second cell mats transfers a precharge voltage to the precharge control circuit. The first and the second cell mats are disposed in the center of the bank.
摘要翻译：半导体存储器件包括一个存储体，一个数据传输线，一个预充电控制电路和一个预充电线。银行包括以矩阵形式布置的多个细胞垫。每个细胞垫具有多个单元电池。布置在单元格块之间的数据传送线传送从单元格单元格中从所选择的单元格矩阵输出的数据信号。布置在组件的边缘上的预充电控制电路控制数据传输线的预充电。布置在第一和第二电池垫之间的预充电线将预充电电压传送到预充电控制电路。第一和第二细胞垫设置在银行的中心。

39. 发明授权

US07642808B2 Impedance adjusting circuit and semiconductor memory device having the same 失效
标题翻译：阻抗调整电路和具有该阻抗调整电路的半导体存储器件
公开(公告)号：US07642808B2
公开(公告)日：2010-01-05
申请号：US12005905
申请日：2007-12-28
申请人： Chun-Seok Jeong , Kang-Seol Lee
发明人： Chun-Seok Jeong , Kang-Seol Lee
IPC分类号： H03K19/003
CPC分类号： H04L25/028
摘要： An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration resistor circuit and generate a second calibration code, the second calibration resistor circuit being connected to a first node; and a transmission line circuit configured to be responsive to a control signal to connect the first node to a pin of a system employing the impedance adjusting circuit.
摘要翻译：阻抗调节电路包括：第一校准电阻器电路，被配置为用外部电阻校准并产生第一校准码; 第二校准电阻器电路，被配置为用第一校准电阻器电路校准并产生第二校准代码，第二校准电阻器电路连接到第一节点; 以及传输线电路，其被配置为响应于控制信号，以将所述第一节点连接到采用所述阻抗调节电路的系统的引脚。

40. 发明申请

US20090273363A1 OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：输出驱动电路，包括输出驱动电路的半导体存储器件以及用于操作半导体存储器件的方法
公开(公告)号：US20090273363A1
公开(公告)日：2009-11-05
申请号：US12165101
申请日：2008-06-30
申请人： Chun-Seok JEONG , Kee-Teok Park
发明人： Chun-Seok JEONG , Kee-Teok Park
IPC分类号： H03K17/16
CPC分类号： H03K19/00361 , H03K17/163 , H03K19/018585
摘要： Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal.
摘要翻译：输出驱动器电路，包括输出驱动器电路的半导体存储器件和用于操作半导体存储器件的方法，包括预驱动器，以根据数据的逻辑值产生上拉控制信号和下拉控制信号输出，并且根据终端电阻设置信息调整和输出上拉控制信号的转换速率和下拉控制信号的转换速率，上拉驱动器响应于输出逻辑高数据而输出逻辑高数据上拉控制信号和下拉驱动器，以响应于下拉控制信号输出逻辑低数据。

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