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21. 发明授权

US4387447A Column and ground select sequence in electrically programmable memory 失效
标题翻译：电可编程存储器中的列和地选序列
公开(公告)号：US4387447A
公开(公告)日：1983-06-07
申请号：US118349
申请日：1980-02-04
申请人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
发明人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
IPC分类号： G11C16/08 , G11C16/10 , H03M7/22 , G11C11/40 , G11C7/00
CPC分类号： G11C16/08 , G11C16/10 , H03M7/22
摘要： An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. To speed up the access time of the memory, the ground select is implemented and applied first, then the output of the ground select is used to generate the column select. In this manner, the biasing sequence for the array can begin before the decode of the column select has been completed.
摘要翻译：具有浮动栅型存储单元的行和列的电可编程存储器阵列在单元列之间采用交替输出线和接地线，从而提供虚拟接地布置。一行由地址输入的一部分选择，另一部分选择一列。所选列的一侧的输出线被激活，另一侧的接地线。差分读出放大器响应所选输出线上的电压和参考电压。为了加快存储器的访问时间，首先实现并应用接地选择，然后使用地选择的输出来生成列选择。以这种方式，阵列的偏置顺序可以在列选择的解码完成之前开始。

22. 发明授权

US4314362A Power down sequence for electrically programmable memory 失效
标题翻译：电可编程存储器的掉电序列
公开(公告)号：US4314362A
公开(公告)日：1982-02-02
申请号：US118287
申请日：1980-02-04
申请人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
发明人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
IPC分类号： G11C16/08 , G11C16/10 , H03M7/22 , G11C7/00
CPC分类号： H03M7/22 , G11C16/08 , G11C16/10
摘要： An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. A power down mode of operation is provided in which current flow in various circuits of the device is greatly reduced. To speed up access time in exiting from power down, the reference voltage input to the sense amplifier is shifted during power down then when exiting returns to its operating value according to a time constant.
摘要翻译：具有浮动栅型存储单元的行和列的电可编程存储器阵列在单元列之间采用交替输出线和接地线，从而提供虚拟接地布置。一行由地址输入的一部分选择，另一部分选择一列。所选列的一侧的输出线被激活，另一侧的接地线。差分读出放大器响应所选输出线上的电压和参考电压。提供了一种断电操作模式，其中大大减少了器件的各种电路中的电流。为了加快从掉电中退出的访问时间，输入到读出放大器的参考电压在掉电期间被移位，然后当退出时根据时间常数返回到其工作值。

23. 发明授权

US3706985A Binary to one out of n converter 失效
标题翻译：二进制转换器
公开(公告)号：US3706985A
公开(公告)日：1972-12-19
申请号：US3706985D
申请日：1971-05-27
申请人： JEUMONT SCHNEIDER
发明人： DARMON JACQUES , COFFRE PHILIPPE
IPC分类号： H03K17/76 , H03M7/22 , H03K13/252
CPC分类号： H03K17/76 , H03M7/22
摘要： A data transmission selector having n inputs and 2n outputs, n being greater than or equal to 2. The data transmission selector comprises: a first selector having p inputs and 2p outputs (p denoting an integer which is at least 1 and less than n), the selector comprising p two-way contacts each operated by a relay winding whose input is one of the selector inputs, each contact point of the moving element of such contacts being connected to the negative side of a d.c. supply while each of the other two contact points a or b is connected to the cathode of 2p 1 diodes, each anode of the diodes being so connected to one of the selector outputs that any of the contact points a or b of a twoway contact is connected via one of the diodes only once to one of the outputs and the contact points a and b of any single twoway contact are not connected to the same output; a second selector having m inputs and 2m outputs comprising 2m-1 two-way contacts operated by m relay windings (whose inputs are the inputs of the second selector) and arranged in a pyramid of m stages (m being equal to n-p), the pyramid apex being connected to the positive side of the d.c. supply, the pyramid base comprising 2m outputs; and connecting circuits between the outputs of the first and second selectors.
摘要翻译：数据传输选择器，其具有n个输入和2n个输出，n大于或等于2.数据传输选择器包括：具有p个输入和2p个输出的第一选择器（p表示至少为1且小于n的整数），所述选择器包括p个双向触头，每个触点由输入为选择器输入之一的继电器绕组操作，这些触点的移动元件的每个接触点连接到直流的负极当其他两个接触点a或b中的每一个连接到2p 1二极管的阴极时，二极管的每个阳极被连接到选择器输出之一，其中任何一个接触点a或b 双向触点仅通过一个二极管连接到输出之一，并且任何单个双向触点的接点a和b未连接到相同的输出; 具有m个输入和2m个输出的第二选择器，其包括由m个继电器绕组（其输入是第二选择器的输入）操作并且布置成m级（m等于np）的金字塔的2m-1个双向触点，金字塔顶点连接到直流的正极供应，包括2m输出的金字塔底座; 以及在第一和第二选择器的输出之间连接电路。

24. 发明授权

US3631465A Fet binary to one out of n decoder 失效
标题翻译： FET二进制到一个N解码器
公开(公告)号：US3631465A
公开(公告)日：1971-12-28
申请号：US3631465D
申请日：1969-05-07
申请人： TELETYPE CORP
发明人： HEEREN RICHARD H
IPC分类号： G11C8/10 , H03K19/00 , H03M7/22 , H03K13/25
CPC分类号： H03K19/00 , G11C8/10 , H03M7/22
摘要： A circuit is described in which eight field effect transistors are interconnected to translate a two-bit binary word into oneout-of-four logic. The description further includes an explanation of how to apply the principles taught herein to build circuits for translating any ''''N''''-bit binary coded word into one out of 2N logic.

25. 发明专利

JPS6110907B2 JPS6110907B2 - 失效
公开(公告)号：JPS6110907B2
公开(公告)日：1986-03-31
申请号：JP5532581
申请日：1981-04-13
申请人： Nippon Electric Co
发明人： MATSUE SHIGEKI
IPC分类号： H03M7/20 , H03K19/094 , H03M7/22
CPC分类号： H03M7/22

26. 发明专利

JPS58194432A One-out-of-n system integrated circuit 失效
标题翻译：一体系统集成电路
公开(公告)号：JPS58194432A
公开(公告)日：1983-11-12
申请号：JP3191583
申请日：1983-03-01
申请人： Itt
发明人： RAINAA BATSUKESU
IPC分类号： H03K19/20 , G06F11/08 , G06F17/40 , H03K5/1534 , H03M7/22
CPC分类号： H03M7/22 , G06F11/085 , H03K5/1534

27. 发明授权

KR1019900000049B1 2단 디코더회로 失效
标题翻译：两级解码器电路
公开(公告)号：KR1019900000049B1
公开(公告)日：1990-01-18
申请号：KR1019850003659
申请日：1985-05-28
申请人： 후지쯔 가부시끼가이샤
发明人： 오까지마요시노리
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , H03M7/22
摘要： A first-stage decoder circuit decodes upper bits of an input signal. A second-stage decoder circuit which is activated by receiving a selected output signalof the first stage, decodes lower bits of the input signal. The first-stage circuit is formed by a logic circuit which carries out selection or non-selection by comparing the input signal with a predetermined threshold level, whilst the second circuit is formed by a diode matrix. The logic circuit comprises a number of emitter-coupled transistors, one of which receives a set threshold level with the others receives an address signal at their respective bases.
摘要翻译：第一级解码器电路解码输入信号的高位。通过接收第一级的所选择的输出信号来激活的第二级解码器电路解码输入信号的低位。第一级电路由逻辑电路形成，逻辑电路通过将输入信号与预定阈值电平进行比较来执行选择或不选择，而第二电路由二极管矩阵形成。逻辑电路包括多个发射极耦合晶体管，其中一个晶体管接收设定的阈值电平，其他发射极耦合晶体管在其各自的基极处接收地址信号。

28. 发明授权

US07002503B2 High speed encoder for high speed analog-to-digital converter 有权
标题翻译：用于高速模数转换器的高速编码器
公开(公告)号：US07002503B2
公开(公告)日：2006-02-21
申请号：US10977954
申请日：2004-10-29
申请人： Ho-Young Lee
发明人： Ho-Young Lee
IPC分类号： H03M1/36
CPC分类号： H03M7/165 , H03M7/22
摘要： A binary encoder which has a fast conversion speed, occupies a small area, and consumes a small amount of power is provided. The binary encoder includes first and second latch transistors, first and second charge transistors, first and second control transistors, first and second discharge transistors, an equalize transistor, and first and second inverters. The first charge transistor charges a first output node to a level of a power voltage in response to a clock signal. The second charge transistor charges a second output node to the level of the power voltage in response to the clock signal. The first discharge transistor discharges a first control node to a level of a ground voltage in response to a first input signal. The second discharge transistor discharges a second control node to the level of the ground voltage in response to a second input signal.
摘要翻译：具有快速转换速度的二进制编码器占用小面积，并且消耗少量的功率。二进制编码器包括第一和第二锁存晶体管，第一和第二充电晶体管，第一和第二控制晶体管，第一和第二放电晶体管，均衡晶体管以及第一和第二反相器。第一充电晶体管响应于时钟信号将第一输出节点充电到电源电压的电平。第二充电晶体管响应于时钟信号而将第二输出节点充电到电源电压的电平。第一放电晶体管响应于第一输入信号将第一控制节点放电至接地电压的电平。第二放电晶体管响应于第二输入信号将第二控制节点放电到接地电压的电平。

29. 发明申请

US20040155803A1 Method for coding a sequence of data bytes via an air interface 有权
公开(公告)号：US20040155803A1
公开(公告)日：2004-08-12
申请号：US10722500
申请日：2003-11-28
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Michael Cuylen
IPC分类号： H03M007/12
CPC分类号： G06K7/10039 , G06K7/0008 , H03M7/22
摘要： A method and associated structures for coding a sequence of data bytes (BY1,BY2), in which two bits (B1, B2) of a data byte form a double bit (D1-D4). Each double bit is represented by a time slot frame (ZR1-ZR4) that has at least four time slots (ZS1-ZS4). The time slots can assume an on or off value (Z1, Z0). The coding is carried out in a time slot frame such that at least one time slot is preloaded with an off value (Z0) at a position (AF). The time slots that have not been preloaded have, at most, one time slot with an on-value in order to form a logic value (00, 01, 10, 11) of a double bit. The method can be used for identification systems (IS), for mobile data memories (DT) and for reader/writers (SLG). Therein, a higher data rate and/or a greater transmission distance between the reader/writer and the mobile data memory is achieved.

30. 发明授权

US5742187A Decoder with reduced architecture 失效
标题翻译：解码器架构减少
公开(公告)号：US5742187A
公开(公告)日：1998-04-21
申请号：US560090
申请日：1995-11-17
申请人： Luigi Pascucci
发明人： Luigi Pascucci
IPC分类号： H03K19/0948 , H03M7/22 , H03K19/084 , H03K19/20
CPC分类号： H03K19/0948 , H03M7/22
摘要： An improved decoder with a reduced architecture that decodes a plurality of input signals that include a least significant input signal. The decoder comprises at least one pair of adjacent logic gates, each of the at least one pair of logic gates receiving at least one logic input signal that is selected from a group of logic signals that include the input signals to the decoder and the inverse of the input signals to the decoder. The logic input signals received by the at least one pair of adjacent logic gates are common to both adjacent logic gates of the pair, except for those logic signals representing the least significant decoder input signal and the inverse of the least significant decoder signal.
摘要翻译：一种具有减小的体系结构的改进的解码器，其对包括最低有效输入信号的多个输入信号进行解码。所述解码器包括至少一对相邻逻辑门，所述至少一对逻辑门中的每一对接收至少一个逻辑输入信号，所述至少一个逻辑输入信号从包括所述解码器的输入信号的逻辑信号组中选出，输入信号到解码器。除了表示最低有效解码器输入信号的那些逻辑信号和最低有效解码器信号的反相之外，由至少一对相邻逻辑门接收的逻辑输入信号对该对的两个相邻逻辑门是公共的。

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