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21. 发明专利

JP3958491B2 Drive circuit 有权
公开(公告)号：JP3958491B2
公开(公告)日：2007-08-15
申请号：JP2000050220
申请日：2000-02-25
申请人：新日本無線株式会社
发明人：智行河野 , 晋一秋田
IPC分类号： H03F3/45 , H03K17/00 , G09G3/36 , H03F1/34 , H03F3/30 , H03K17/687 , H03K19/0175
CPC分类号： H03F3/3023 , G09G3/36 , G09G3/3688 , G09G3/3696 , G09G2310/0291 , G09G2330/02 , H03F3/45188 , H03F3/45192 , H03F2203/30018 , H03F2203/30036 , H03F2203/30057 , H03F2203/45301 , H03F2203/45486 , H03F2203/45508 , H03F2203/45644 , H03F2203/45658

22. 发明授权

US08054131B2 Transconductor circuit 有权
标题翻译：跨导电路
公开(公告)号：US08054131B2
公开(公告)日：2011-11-08
申请号：US13006246
申请日：2011-01-13
申请人： Sebastian Zeller
发明人： Sebastian Zeller
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F1/0261 , H03F3/195 , H03F3/4508 , H03F2200/294 , H03F2200/36 , H03F2200/375 , H03F2203/45318 , H03F2203/45352 , H03F2203/45362 , H03F2203/45382 , H03F2203/45384 , H03F2203/45392 , H03F2203/45486 , H03F2203/45496
摘要： A transconductor circuit, particularly according to the multi-tanh principle, having a first input node and a second input node, a first differential amplifier coupled to the first and second input nodes, and having a first offset voltage, and a second differential amplifier coupled to the first and second input nodes, and having a second offset voltage different from the first offset voltage. A first resistance circuit is coupled between the first differential amplifier and at least one current source, and a second resistance circuit is coupled between the second differential amplifier and the at least one current source. Varying of the current sources enables control of the transconductance without degrading linearity.
摘要翻译：具有第一输入节点和第二输入节点的多导体电路特别是多导体电路，耦合到第一和第二输入节点并且具有第一偏移电压的第一差分放大器和耦合到第一输入节点的第二差分放大器到第一和第二输入节点，并且具有不同于第一偏移电压的第二偏移电压。第一电阻电路耦合在第一差分放大器和至少一个电流源之间，第二电阻电路耦合在第二差分放大器和至少一个电流源之间。电流源的变化使得可以控制跨导而不降低线性度。

23. 发明申请

US20110175759A1 OPERATIONAL AMPLIFIER AND PIPELINE AD CONVERTER 审中-公开
标题翻译：操作放大器和管道AD转换器
公开(公告)号：US20110175759A1
公开(公告)日：2011-07-21
申请号：US13079259
申请日：2011-04-04
申请人： Daisuke NOMASAKI , Koji Oka
发明人： Daisuke NOMASAKI , Koji Oka
IPC分类号： H03M1/02
CPC分类号： H03F3/45183 , H01L27/0629 , H01L27/0811 , H01L27/088 , H03F2203/45352 , H03F2203/45371 , H03F2203/45486 , H03M1/0682 , H03M1/0695 , H03M1/442
摘要： A differential voltage interconnect (W101a) electrically connects the gate electrode of a transistor to be used among differential transistors (T101a, T101a, . . . ) to an input node receiving an input voltage (Vinn), and a differential voltage interconnect (W101b) electrically connects the gate electrode of a transistor to be used among differential transistors (T101b, T101b, . . . ) to an input node receiving an input voltage (Vinp). A bias voltage interconnect (W102) electrically connects the gate electrode of a transistor to be used among current source transistors (T102, T102, . . . ) to a bias node receiving a bias voltage (VBN), and a bias voltage interconnect (W103) electrically connects the gate electrodes of transistors to be used among load transistors (T103a, T103a, . . . , T103b, T103b, . . . ) to a bias node receiving a bias voltage (VBP).
摘要翻译：差分电压互连（W101a）将要用于差分晶体管（T101a，T101a ...等）的晶体管的栅极电连接到接收输入电压（Vinn）的输入节点和差分电压互连（W101b）将待使用的晶体管的栅电极（T101b，T101b ...）电连接到接收输入电压（Vinp）的输入节点。偏置电压互连（W102）将要用于电流源晶体管（T102，T102 ......）中的晶体管的栅极电连接到接收偏置电压（VBN）的偏置节点和偏置电压互连（W103））将负载晶体管（T103a，T103a，...，T103b，T103b ...等）中使用的晶体管的栅极电连接到接收偏置电压（VBP）的偏置节点。

24. 发明授权

US07940121B2 Operational amplifier and pipeline AD converter 失效
标题翻译：运算放大器和管线AD转换器
公开(公告)号：US07940121B2
公开(公告)日：2011-05-10
申请号：US12445003
申请日：2008-07-30
申请人： Daisuke Nomasaki , Koji Oka
发明人： Daisuke Nomasaki , Koji Oka
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H01L27/0629 , H01L27/0811 , H01L27/088 , H03F2203/45352 , H03F2203/45371 , H03F2203/45486 , H03M1/0682 , H03M1/0695 , H03M1/442
摘要： A differential voltage interconnect (W101a) electrically connects the gate electrode of a transistor to be used among differential transistors (T101a, T101a, . . . ) to an input node receiving an input voltage (Vinn), and a differential voltage interconnect (W101b) electrically connects the gate electrode of a transistor to be used among differential transistors (T101b, T101b, . . . ) to an input node receiving an input voltage (Vinp). A bias voltage interconnect (W102) electrically connects the gate electrode of a transistor to be used among current source transistors (T102, T102, . . . ) to a bias node receiving a bias voltage (VBN), and a bias voltage interconnect (W103) electrically connects the gate electrodes of transistors to be used among load transistors (T103a, T103a, . . . , T103b, T103b, . . . ) to a bias node receiving a bias voltage (VBP).
摘要翻译：差分电压互连（W101a）将要用于差分晶体管（T101a，T101a ...等）的晶体管的栅极电连接到接收输入电压（Vinn）的输入节点和差分电压互连（W101b）将待使用的晶体管的栅电极（T101b，T101b ...）电连接到接收输入电压（Vinp）的输入节点。偏置电压互连（W102）将要用于电流源晶体管（T102，T102 ......）中的晶体管的栅极电连接到接收偏置电压（VBN）的偏置节点和偏置电压互连（W103 ）将负载晶体管（T103a，T103a，...，T103b，T103b ...等）中使用的晶体管的栅极电连接到接收偏置电压（VBP）的偏置节点。

25. 发明授权

US07876153B1 Transconductor circuit 有权
公开(公告)号：US07876153B1
公开(公告)日：2011-01-25
申请号：US12606374
申请日：2009-10-27
申请人： Sebastian Zeller
发明人： Sebastian Zeller
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F1/0261 , H03F3/195 , H03F3/4508 , H03F2200/294 , H03F2200/36 , H03F2200/375 , H03F2203/45318 , H03F2203/45352 , H03F2203/45362 , H03F2203/45382 , H03F2203/45384 , H03F2203/45392 , H03F2203/45486 , H03F2203/45496
摘要： A transconductor circuit, particularly according to the multi-tanh principle, having a first input node and a second input node, a first differential amplifier coupled to the first and second input nodes, and having a first offset voltage, and a second differential amplifier coupled to the first and second input nodes, and having a second offset voltage different from the first offset voltage. A first resistance circuit is coupled between the first differential amplifier and at least one current source, and a second resistance circuit is coupled between the second differential amplifier and the at least one current source. Varying of the current sources enables control of the transconductance without degrading linearity.

26. 发明授权

US07643573B2 Power management in a data acquisition system 有权
标题翻译：数据采集系统中的电源管理
公开(公告)号：US07643573B2
公开(公告)日：2010-01-05
申请号：US11378009
申请日：2006-03-17
申请人： Murari Kejariwal , John R. Coupe, II
发明人： Murari Kejariwal , John R. Coupe, II
IPC分类号： H04L25/03 , H04L27/08 , H04L7/00
CPC分类号： H03F3/45188 , H03F3/45475 , H03F2200/331 , H03F2203/45032 , H03F2203/45371 , H03F2203/45396 , H03F2203/45486 , H03F2203/45504 , H03F2203/45631 , H03F2203/45634 , H03F2203/45726 , H03G1/0029 , H03G1/0088 , H03M1/129
摘要： A data acquisition system includes a programmable gain amplifier, an analog-to-digital converter, a filter, and control circuitry. The programmable gain amplifier is operatively connected to receive an analog input signal on its input and generates an amplified signal on its output in accordance with gain control signals. The analog-to-digital converter is operatively connected to receive the amplified signal from the amplifier and generates a digitized signal on its output. The filter is operatively connected to receive the digitized signal from the converter and generates a filtered digital signal on its output. The control circuitry is operatively connected to the amplifier and to the converter and is also responsive to the gain control signals for dynamically adjusting power between the amplifier and converter when the gain control signals are changed.
摘要翻译：数据采集系统包括可编程增益放大器，模数转换器，滤波器和控制电路。可编程增益放大器可操作地连接以在其输入上接收模拟输入信号，并根据增益控制信号在其输出上产生放大信号。模数转换器可操作地连接以从放大器接收放大的信号，并在其输出端产生数字化信号。滤波器可操作地连接以接收来自转换器的数字化信号，并在其输出端产生滤波后的数字信号。控制电路可操作地连接到放大器和转换器，并且当增益控制信号改变时也响应于增益控制信号来动态调整放大器和转换器之间的功率。

27. 发明申请

US20070069817A1 ADAPTABLE VOLTAGE CONTROL FOR A VARIABLE GAIN AMPLIFIER 有权
标题翻译：可变增益放大器的适应电压控制
公开(公告)号：US20070069817A1
公开(公告)日：2007-03-29
申请号：US11559195
申请日：2006-11-13
申请人： Mario Caresosa , Guangming Yin
发明人： Mario Caresosa , Guangming Yin
IPC分类号： H03G3/10
CPC分类号： H03F3/4569 , H03F3/45197 , H03F3/45744 , H03F2200/78 , H03F2203/45074 , H03F2203/45086 , H03F2203/45482 , H03F2203/45486 , H03G1/0088 , H03G3/3036 , H03G3/3052
摘要： A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.
摘要翻译：一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

28. 发明授权

US08514020B2 Temperature compensated feedforward linearizer 有权
标题翻译：温度补偿前馈线性化器
公开(公告)号：US08514020B2
公开(公告)日：2013-08-20
申请号：US13220339
申请日：2011-08-29
申请人： Thomas E. Collins, III , Gregory M. Flewelling
发明人： Thomas E. Collins, III , Gregory M. Flewelling
IPC分类号： H03F1/00 , H03F3/04
CPC分类号： H03F1/3211 , H03F3/45089 , H03F3/45484 , H03F2200/447 , H03F2203/45486 , H03F2203/45504
摘要： A feedforward linearizer device is disclosed. The device includes a main amplifier, and a linearizing amplifier operatively coupled to the main amplifier. A first reference generator is operatively coupled to the main amplifier by a first reference node. A second reference generator is operatively coupled to the linearizing amplifier by a second reference node, and is configured to cause an optimal linearizing amplifier output current for each of a plurality of temperatures. In one such case, the second reference generator is configured to cause an optimal linearizing amplifier output current for each of a plurality of temperatures based on a corresponding optimal ratio of main amplifier output current and linearizing amplifier output current. The linearizing amplifier may be configured with a tunable current source that is controlled by the second reference generator, or a current source having a fixed total transistor area (not tunable).
摘要翻译：公开了一种前馈线性化装置。该器件包括主放大器和可操作地耦合到主放大器的线性放大器。第一参考发生器通过第一参考节点可操作地耦合到主放大器。第二参考发生器通过第二参考节点可操作地耦合到线性化放大器，并且被配置为为多个温度中的每一个引起最佳的线性化放大器输出电流。在一种这种情况下，第二参考发生器被配置为基于主放大器输出电流和线性化放大器输出电流的对应最佳比率，为多个温度中的每一个引起最佳线性化放大器输出电流。线性化放大器可以配置有由第二参考发生器控制的可调电流源，或者具有固定的总晶体管面积（不可调）的电流源。

29. 发明申请

US20110109390A1 TRANSCONDUCTOR CIRCUIT 有权
标题翻译： TRANSCONDUCTOR电路
公开(公告)号：US20110109390A1
公开(公告)日：2011-05-12
申请号：US13006246
申请日：2011-01-13
申请人： Sebastian Zeller
发明人： Sebastian Zeller
IPC分类号： H03F3/45
CPC分类号： H03F3/45085 , H03F1/0261 , H03F3/195 , H03F3/4508 , H03F2200/294 , H03F2200/36 , H03F2200/375 , H03F2203/45318 , H03F2203/45352 , H03F2203/45362 , H03F2203/45382 , H03F2203/45384 , H03F2203/45392 , H03F2203/45486 , H03F2203/45496
摘要： A transconductor circuit, particularly according to the multi-tanh principle, having a first input node and a second input node, a first differential amplifier coupled to the first and second input nodes, and having a first offset voltage, and a second differential amplifier coupled to the first and second input nodes, and having a second offset voltage different from the first offset voltage. A first resistance circuit is coupled between the first differential amplifier and at least one current source, and a second resistance circuit is coupled between the second differential amplifier and the at least one current source. Varying of the current sources enables control of the transconductance without degrading linearity.
摘要翻译：具有第一输入节点和第二输入节点的多导体电路特别是多导体电路，耦合到第一和第二输入节点并且具有第一偏移电压的第一差分放大器和耦合到第一输入节点的第二差分放大器到第一和第二输入节点，并且具有不同于第一偏移电压的第二偏移电压。第一电阻电路耦合在第一差分放大器和至少一个电流源之间，第二电阻电路耦合在第二差分放大器与至少一个电流源之间。电流源的变化使得可以控制跨导而不降低线性度。

30. 发明授权

US07826188B2 Methods, design structures, and systems for current mode logic (CML) differential driver ESD protection circuitry 失效
标题翻译：电流模式逻辑（CML）差分驱动器ESD保护电路的方法，设计结构和系统
公开(公告)号：US07826188B2
公开(公告)日：2010-11-02
申请号：US12140485
申请日：2008-06-17
申请人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H03F3/45188 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F2203/45466 , H03F2203/45486 , H03F2203/45504
摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.
摘要翻译：在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。

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