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21. 发明申请

US20140233304A1 SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME 有权
标题翻译：半导体器件及其控制方法
公开(公告)号：US20140233304A1
公开(公告)日：2014-08-21
申请号：US14343325
申请日：2012-09-07
申请人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
发明人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G06F9/30098 , G06F9/30101 , G06F9/4418 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C14/0081 , G11C2207/007 , H03K17/24
摘要： A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.
摘要翻译：半导体器件包括非易失性寄存器，每个寄存器包括用于以易失性方式保存数据的保持电路和非易失性元件。一个地址分配给每个非易失性寄存器。非易失性寄存器控制电路执行控制，使得响应于写指令，保持在保持电路中的数据被写入具有由指令指定的地址的非易失性寄存器中的非易失性元件，并响应于保持在非易失性元件中的数据的加载指令被保持在具有由指令指定的地址的非易失性寄存器中的保持电路中。

22. 发明申请

US20100157705A1 Register file circuits with P-type evaluation 有权
标题翻译：注册文件电路与P型评估
公开(公告)号：US20100157705A1
公开(公告)日：2010-06-24
申请号：US12317000
申请日：2008-12-18
申请人： Bibiche Geuskens , Ataur Patwary , Eric Kwesi Donkoh , Muhammad Khellah , Tanay Karnik
发明人： Bibiche Geuskens , Ataur Patwary , Eric Kwesi Donkoh , Muhammad Khellah , Tanay Karnik
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C2207/007 , H03K19/01742
摘要： Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such “normally Low” evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates.
摘要翻译：这里提供了一种新的RF实现。不是为其一个或多个评估节点使用预充电的高节点，而是在评估之前使用放电（低）的评估（或评估）节点，并在放电状态下进行评估。在一些实施例中，利用这种“通常为低”的评估节点，如果逻辑如此指示，则使用上拉堆栈设备而不是下拉设备在评估阶段期间对评估节点充电。

23. 发明申请

US20050099205A1 REGISTER-FILE BIT-READ METHOD AND APPARATUS 失效
标题翻译：寄存器 - 文件位读取方法和装置
公开(公告)号：US20050099205A1
公开(公告)日：2005-05-12
申请号：US10703016
申请日：2003-11-06
申请人： Sam Chu , Peter Klim , Michael Lee , Jose Paredes
发明人： Sam Chu , Peter Klim , Michael Lee , Jose Paredes
IPC分类号： G06F7/38 , G11C7/10 , H03K19/0175 , H03K19/173
CPC分类号： G11C7/1048 , G11C2207/007
摘要： A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.
摘要翻译：寄存器 - 文件位读取装置包括：解码器，可操作用于接收多个地址位信号，并响应地在M个选择行之一中断言选择信号。每个选择行对应于M个寄存器文件单元中的相应一个。该装置还包括具有Q个输出节点和M个选择器的多路复用器。每个选择器耦合到选择线之一，并选择线对应的寄存器文件单元。选择器处于Q组中，每组耦合到多路复用器的输出节点中的相应一个。该装置还包括具有Q输入的输出逻辑门，耦合到多路复用器输出节点中的相应一个。多路复用器包括Q个上拉，其中每个Q上拉耦合到多路复用器输出节点中的相应一个，并且可操作以响应于地址位信号之一驱动其多路复用器输出节点。

24. 发明公开

EP3355307A1 METHODS AND APPARATUS FOR REUSING LOOKUP TABLE RANDOM-ACCESS MEMORY (LUTRAM) ELEMENTS AS CONFIGURATION RANDOM-ACCESS MEMORY (CRAM) ELEMENTS 有权转让
公开(公告)号：EP3355307A1
公开(公告)日：2018-08-01
申请号：EP18150319.4
申请日：2018-01-04
申请人： INTEL Corporation
发明人： CHANDLER, Trevis , KO, JUNG , DUONG, Kenneth , SIKDAR, Dipak
IPC分类号： G11C8/10 , G11C7/12 , G11C8/16 , G11C11/418 , H03K19/177 , G11C11/412
CPC分类号： G11C11/418 , G11C7/12 , G11C8/10 , G11C8/16 , G11C11/412 , G11C2207/007 , H03K19/17728
摘要： A programmable integrated circuit may include configuration random-access memory (CRAM) cells and lookup table random-access memory (LUTRAM) cells. The programmable integrated circuit may include a CRAM column and at least two LUTRAM columns, a first portion of which is operable as LUTRAM cells and a second portion of which is reused as CRAM cells. Each of the memory cells have a configuration write port and a read port. The configuration write ports of the first portion may be gated, whereas the configuration write ports of the second portion lack gating logic. The read port of the memory cells in the LUTRAM columns may be masked only when the first portion of cells are operated in RAM mode and are currently being accessed.

25. 发明授权

EP1488428B1 REGISTERZELLE UND VERFAHREN ZUM SCHREIBEN AUF DIE REGISTERZELLE 有权
标题翻译：寄存器单元和方法写在寄存器单元
公开(公告)号：EP1488428B1
公开(公告)日：2006-09-06
申请号：EP03712035.9
申请日：2003-03-17
申请人： Infineon Technologies AG
发明人： ELBE, Astrid , FISCHER, Wieland , JANSSEN, Norbert , ROEMER, Tanja , SEDLAK, Holger , SEIFERT, Jean-Pierre
IPC分类号： G11C11/41
CPC分类号： G11C7/22 , G11C2207/007 , G11C2207/2227
摘要： The invention relates to a register cell which comprises a first input (10) for a data unit to be written into said register cell. The register cell further comprises a second input (12) for a negated data unit to be written into the register cell. A first pair (14) of cross-coupled inverters (14a, 14b) can be coupled with the first input (10) as the first memory circuit. A second pair of cross-coupled inverters (16a, 16b) can be coupled with the second input (12) as the second memory circuit. The use of two cross-coupled pairs of inverters allows to initialize (30) the first input (10) and the second input (12) of the register either at a high voltage status (precharge) or at a low voltage status (discharge) in such a manner as to render the power consumption of the register cell from one cycle to the next more uniform.

26. 发明申请

US20190080781A1 STORAGE DEVICE, OPERATION PROCESSING DEVICE, AND CONTROL METHOD OF STORAGE DEVICE 审中-公开
公开(公告)号：US20190080781A1
公开(公告)日：2019-03-14
申请号：US16120807
申请日：2018-09-04
申请人： FUJITSU LIMITED
发明人： Soichiro NAKAMURA , Tomohiro TANAKA
IPC分类号： G11C29/38 , G11C7/10 , G11C7/24 , G11C29/36
CPC分类号： G11C29/38 , G11C7/1006 , G11C7/1075 , G11C7/24 , G11C29/1201 , G11C29/14 , G11C29/32 , G11C29/36 , G11C29/46 , G11C2029/3202 , G11C2207/007
摘要： A storage device includes: a first disabling unit configured to output write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by a first holding unit do not match; a second holding unit configured to hold sets of the plurality of write addresses held by the first holding unit and the plurality of write enable signals output by the first disabling unit; a second disabling unit configured to output one write enable signal of the plurality of write enable signals held by the second holding unit without change in a test mode; and a third holding unit configured to write data in accordance with sets of the plurality of write addresses held by the second holding unit and the plurality of write addresses output by the second disabling unit.

27. 发明授权

US09786350B2 Memory device 有权
公开(公告)号：US09786350B2
公开(公告)日：2017-10-10
申请号：US14208714
申请日：2014-03-13
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Takuro Ohmaru
IPC分类号： G11C14/00 , G11C11/24 , G11C11/403 , H01L27/12 , H01L27/1156
CPC分类号： G11C11/24 , G11C11/403 , G11C14/0054 , G11C2207/007 , H01L27/1156 , H01L27/1225
摘要： A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform logic inversion, a selection circuit, a first switch, a second switch, and a third switch. The second memory circuit includes a first transistor in which a channel formation region is provided in an oxide semiconductor film, a second transistor, and a capacitor to which a potential is supplied through the first transistor.

28. 发明授权

US09251875B1 Register file circuit and method for improving the minimum operating supply voltage 有权
标题翻译：寄存器文件电路和方法，用于提高最小工作电源电压
公开(公告)号：US09251875B1
公开(公告)日：2016-02-02
申请号：US14499052
申请日：2014-09-26
申请人： QUALCOMM Incorporated
发明人： Francois Ibrahim Atallah , Jihoon Jeong , Keith Alan Bowman , Amey Sudhir Kulkarni , Jason Philip Martzloff , Joshua Lance Puckett
IPC分类号： G11C7/22 , G11C7/12 , G11C5/06
CPC分类号： G11C7/12 , G11C5/06 , G11C5/147 , G11C7/22 , G11C11/419 , G11C2207/007
摘要： A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.
摘要翻译：根据本公开的一些示例的寄存器文件电路可以包括存储器单元，标头晶体管电路和驱动器电路。标头晶体管电路可以包括与存储单元的PFET串联的一个或多个PFET头，用于被写入的行的PFET头的栅极被来自驱动器电路的脉冲写入信号控制。在本公开的一些示例中，标题晶体管电路可以包括插入在虚拟vdd和地之间的NFET下拉以放电虚拟vdd节点，以减少在写入操作期间的争用，并且与PFET头并联的钳位NFET 将虚拟vdd节点钳位到略低于存储单元中的上拉PFET的阈值电压，以确保上拉PFET几乎不会关闭，并防止虚拟vdd节点一直向地面放电。

29. 发明申请

US20140226395A1 Latch-based Array with Robust Design-for-Test (DFT) Features 有权
标题翻译：具有鲁棒设计测试（DFT）功能的基于锁存器的阵列
公开(公告)号：US20140226395A1
公开(公告)日：2014-08-14
申请号：US13767788
申请日：2013-02-14
申请人： QUALCOMM INCORPORATED
发明人： Ramaprasath Vilangudipitchai , Gaurav Bhargava , Ohsang Kwon
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C2207/007
摘要： A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.
摘要翻译：基于锁存器的存储器包括以行和列排列的多个从锁存器。每列从锁存器从相应的主锁存器接收锁存的数据信号。每行包括时钟门控电路和相应的复位电路。如果一行对于写操作有效，则活动行的时钟选通电路将写时钟传递到活动行的从锁存器。相反，用于非活动行的时钟门控电路通过将第一时钟状态的写入时钟的保持版本传递到非活动行的从锁存器来将写时钟门禁到非活动行的从锁存器。当复位信号被断言时，每个复位电路通过将第一时钟状态下的写入时钟的保持版本传送到复位电路行中的从锁存器来对写时钟进行门控。

30. 发明授权

US08767492B2 Methods and systems to read register files with un-clocked read wordlines and clocked bitlines, and to pre-charge a biteline to a configurable voltage 有权
标题翻译：使用非时钟读取字线和时钟位线读取寄存器文件的方法和系统，并将位线预充电到可配置电压
公开(公告)号：US08767492B2
公开(公告)日：2014-07-01
申请号：US12776264
申请日：2010-05-07
申请人： Eric Kwesi Donkoh
发明人： Eric Kwesi Donkoh
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C2207/007
摘要： A method and system to improve the operations of a memory device by reducing its bit line leakage, power consumption, and read access time. The memory device has a static read word line for each of its bit cells and domino logic for each of its bit line. Each bit line of the memory device is coupled with a gating logic that is activated using a clocked signal. This eases the timing requirement of the read word lines of the memory device and the read word lines do not form the critical path of the access time of the memory device. The leakage current of the memory device in inactive mode is reduced by switching off the pre-charge circuit and/or the keeper circuit of each bit line. Each bit line is pre-charged on demand prior to the evaluation of each bit line.
摘要翻译：通过减少其位线泄漏，功耗和读取访问时间来改善存储器件的操作的方法和系统。存储器件具有用于其位单元中的每一个的静态读取字线和其位线中的每一个的多米诺逻辑。存储器件的每个位线与使用时钟信号激活的门控逻辑耦合。这减轻了存储器件的读取字线的时序要求，并且读取的字线不会形成存储器件的访问时间的关键路径。通过关闭每个位线的预充电电路和/或保持器电路来减少存储器件在非活动模式下的漏电流。在评估每个位线之前，每个位线都是按需预充电的。

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