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21. 发明公开

EP0595050A2 Sense amplifier clock driver 失效转让
标题翻译：感应放大器时钟驱动器
公开(公告)号：EP0595050A2
公开(公告)日：1994-05-04
申请号：EP93115771.3
申请日：1993-09-30
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Hardee, Kim C.
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/065
摘要： A method and apparatus for generating two control signals (LPB, LNB) to activate local sense amplifier driver transistors (140, 142) is described. The rise and fall times of these signals as well as their levels keep the sense speed and peak currents as constant as possible over the specified voltage and temperature ranges. This is achieved preferably by using current sources (208, 222) based on resistors (507, 512; 500, 502) to control the rise/fall times and current mirrors or modeling circuits (212,230) to set the voltage levels. Preferably circuitry (230, 528; 212, 490) is provided to determine when LNB and LPB reach intermediate and full voltage levels. The timing is set to spread out the current peak into three separate smaller peaks.
摘要翻译：描述了用于生成两个控制信号（LPB，LNB）以激活本地读出放大器驱动器晶体管（140,142）的方法和设备。这些信号的上升和下降时间以及它们的电平在指定的电压和温度范围内保持感测速度和峰值电流尽可能恒定。这优选地通过使用基于电阻器（507,512; 500,502）的电流源（208,222）来控制上升/下降时间以及电流镜或者建模电路（212,230）来设置电压电平。优选地，提供电路（230,528; 212,490）以确定LNB和LPB何时达到中间和全电压电平。时间设置为将当前峰分散为三个单独的较小峰。

22. 发明公开

EP0530792A3 Bit line and cell plate clamp circuit particularly for a DRAM 失效转让
标题翻译：位线和电池板钳位电路特别用于DRAM
公开(公告)号：EP0530792A3
公开(公告)日：1993-08-11
申请号：EP92115058.7
申请日：1992-09-03
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Eaton, Sheffield S., Jr.
IPC分类号： G11C11/407 , G11C11/409
CPC分类号： G11C11/4074 , G11C11/4094
摘要： A supply circuit (40) providing an intermediate voltage between Vss and Vcc for a DRAM is coupled to both the cell capacitor plates and the bit line clamp transistors. The supply circuit includes a logic circuit (42) which ANDs the equilibration signal and a restore complete signal thereby to provide a timing signal in the initial portion of the precharge epoch. The timing signal turns on first and second transistors (46, 44) which operate as a load to develop a voltage at first and second nodes (45, 47). The voltage so developed is a transition voltage above the target holding voltage. This voltage is stored on a storage capacitor (52), coupled to the gate electrode of a drive transistor (50) and transistor (44). The drive transistor selectively couples operating voltage (VCC) to the hold line (22). After the logic circuit turns off, the offset voltage which has been stored on the capacitor (52) controls the drive transistor (50) to couple the target holding voltage to the holding line.

23. 发明授权

EP0585755B1 Apparatus providing a MOS temperature compensated voltage reference for low voltages and wide voltage ranges 失效转让
标题翻译：装置，用于生成经温度补偿的基准电压MOS用于低电压和高的工作电压范围
公开(公告)号：EP0585755B1
公开(公告)日：1999-03-10
申请号：EP93113334.2
申请日：1993-08-20
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Cordoba, Michael V. , Hardee, Kim C. , Butler, Douglas B.
IPC分类号： G05F3/24
CPC分类号： G05F3/245 , G05F3/247 , Y10S323/907

24. 发明授权

EP0609577B1 Dram variable row select 失效转让
标题翻译： DRAM可变字线选择
公开(公告)号：EP0609577B1
公开(公告)日：1999-01-07
申请号：EP93203125.5
申请日：1993-11-09
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Parris, Michael C.
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/406 , G11C11/408

25. 发明授权

EP0747799B1 Transistor programmable voltage reference generator 失效
标题翻译：可编程晶体管的参考电压发生器
公开(公告)号：EP0747799B1
公开(公告)日：1998-12-23
申请号：EP96108653.5
申请日：1996-05-30
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Egging, Tim P.
IPC分类号： G05F3/20
CPC分类号： G05F3/247

26. 发明公开

EP0852381A2 Sense amplifier with local write drivers 失效
标题翻译： Leseverstärkermit lokalen Schreibtreibern
公开(公告)号：EP0852381A2
公开(公告)日：1998-07-08
申请号：EP98102694.1
申请日：1993-09-30
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Hardee, Kim C.
IPC分类号： G11C7/06
CPC分类号： G11C7/1096 , G11C7/065 , G11C7/1078
摘要： A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one (140) connecting the P channel transistors (112, 114) to VCC; the other (142) connecting the N channel transistors (142) to VSS. A read amplifier circuit (150-156) is provided within each sense amplifier and is operated by read control signals (DR, DRB, YR). Internal nodes of the latch of the sense amplifier are coupled by pass transistors (122, 124) that are responsive to column write control signals (YW). Local data write driver transistors (128, 130, 132, 134) are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals (DW, DWB). A relatively wider power line (184) is coupled to the drive transistors (140) to provide VCC thereto, and a narrower line (181) is used to control those first sense amplifier drive transistors (140). Corresponding wide and narrow lines (190, 186) are used for the second local sense amplifier drive transistors which couple the N channel transistors to ground. Each sense amplifier may be shared between first and second pairs of bit lines (220, 222; 224, 226) through the use of isolation transistors 232, 234, 238, 240) and a corresponding isolation signal (ISOL, ISOR).
摘要翻译：描述了使用CMOS技术的非常高密度集成电路存储器的读出放大器。每个读出放大器包括第一和第二本地读出放大器驱动晶体管，一个（140）将P沟道晶体管（112,114）连接到VCC; 另一个（142）将N沟道晶体管（142）连接到VSS。读取放大器电路（150-156）设置在每个读出放大器内并由读取控制信号（DR，DRB，YR）操作。读出放大器的锁存器的内部节点由响应于列写入控制信号（YW）的传输晶体管（122,124）耦合。还提供本地数据写入驱动器晶体管（128,130,132,134）以响应于另外的数据写入控制信号（DW，DWB）选择性地将传输晶体管耦合到VCC-Vt或VSS。相对较宽的电源线（184）耦合到驱动晶体管（140）以向其提供VCC，并且使用较窄的线（181）来控制那些第一读出放大器驱动晶体管（140）。相应的宽和窄线（190,186）用于将N沟道晶体管耦合到地的第二局部读出放大器驱动晶体管。每个读出放大器可以通过使用隔离晶体管232,234,238,240以及对应的隔离信号（ISOL，ISOR）在第一和第二对位线（220,222; 224,226）之间共享。

27. 发明公开

EP0750310A1 High speed differential current sense amplifier with positive feedback 失效
标题翻译： Hochgeschwindigkeitsdifferentialstromleseverstärkermit positienRückmeldung
公开(公告)号：EP0750310A1
公开(公告)日：1996-12-27
申请号：EP95109683.3
申请日：1995-06-22
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Faue, Jon Allan
IPC分类号： G11C7/06
CPC分类号： H03K3/012 , G11C7/062 , G11C7/065 , G11C2207/063
摘要： Positive feedback increases switching speeds and negative feedback prevents the voltage at the inputs (12, 14) from varying too far in a sense amplifier (20) used to sense voltage differentials on bit lines or data lines of semiconductor memories, or elsewhere. Switching speeds improve without increased current consumption.
摘要翻译：正反馈增加了开关速度和负反馈，防止在用于感测半导体存储器或其他地方的位线或数据线上的电压差的读出放大器（20）中输入端（12,14）处的电压变化太远。切换速度提高而不增加电流消耗。

28. 发明公开

EP0595050A3 Sense amplifier clock driver 失效转让
标题翻译：时钟驱动器的读出放大器。
公开(公告)号：EP0595050A3
公开(公告)日：1994-10-26
申请号：EP93115771.3
申请日：1993-09-30
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Hardee, Kim C.
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/065
摘要： A method and apparatus for generating two control signals (LPB, LNB) to activate local sense amplifier driver transistors (140, 142) is described. The rise and fall times of these signals as well as their levels keep the sense speed and peak currents as constant as possible over the specified voltage and temperature ranges. This is achieved preferably by using current sources (208, 222) based on resistors (507, 512; 500, 502) to control the rise/fall times and current mirrors or modeling circuits (212,230) to set the voltage levels. Preferably circuitry (230, 528; 212, 490) is provided to determine when LNB and LPB reach intermediate and full voltage levels. The timing is set to spread out the current peak into three separate smaller peaks.

29. 发明公开

EP0563521A3 Low power DRAM 失效
标题翻译：低功率DRAM
公开(公告)号：EP0563521A3
公开(公告)日：1994-09-21
申请号：EP93101104.3
申请日：1993-01-26
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Eaton, Sheffield S. Jr.
IPC分类号： G11C11/407 , G11C11/409
CPC分类号： G11C11/4074
摘要： In a DRAM, a logic "1" is redefined as the minimum VCC value minus one threshold voltage. The word line (16) is not bootstrapped. This intermediate voltage is applied via the sense amplifier (22) to the bit lines (14, 14') during refresh.The intermediate value is controlled preferably by a comparator (34) controlling a driver (36). Even when the power supply voltage rises, the intermediate voltage is held constant by comparison to a fixed reference voltage (Vref). Operating current is substantially reduced because less power is required to write data into the memory cells (12, 18; 12', 18'), since a controlled lower voltage is used.

30. 发明公开

EP0609497A2 A device and method for maintaining a high voltage for low power applications 失效转让
标题翻译：装置和用于保持高电压到低电压用途的方法。
公开(公告)号：EP0609497A2
公开(公告)日：1994-08-10
申请号：EP93117388.4
申请日：1993-10-27
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Cordoba, Michael
IPC分类号： G11C5/14
CPC分类号： G05F3/205 , G05F1/465 , G11C5/14 , G11C5/145 , G11C5/146
摘要： A voltage generator for low power applications includes a circuit for generating, controlling and maintaining a high voltage (VCCP) for low power applications in an integrated circuit. The circuit includes separate standby circuits (110, 300, 478) and active circuits (200, 478', 500) for pumping V CCP of a DRAM under different circumstances. The standby and active circuits operate independently of one another, but may operate simultaneously, to pump charge to V CCP . The standby circuit is generally a low power circuit activated in response to power up and leakage current conditions to maintain the high voltage (V CCP ). The active circuit is generally a larger circuit and can pump more current. The active circuit is generally responsive to the word lines being driven. Accordingly, the voltage generator can maintain V CCP while minimizing power consumption in DRAM.
摘要翻译：对于低功率应用的电压发生器包括用于产生，控制和维护用于在集成电路的低功率应用的高电压（VCCP）的电路。该电路包括用于泵送在不同情况下的DRAM的VCCP单独的备用电路（110，300，478）和有源电路（200，478”，500）。待机和有源电路操作unabhängig彼此的，但也可以同时操作，以泵送电荷VCCP。备用电路是基因集会低功率电路响应激活上电和漏电流条件下保持高电压（VCCP）。有源电路是基因拉力更大的电路和可泵更大的电流。有源电路是基因反弹响应于被驱动的字线。因此，电压发生器可以维持VCCP而在DRAM最小化功耗。

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