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1. 发明授权

EP0585755B1 Apparatus providing a MOS temperature compensated voltage reference for low voltages and wide voltage ranges 失效转让
标题翻译：装置，用于生成经温度补偿的基准电压MOS用于低电压和高的工作电压范围
公开(公告)号：EP0585755B1
公开(公告)日：1999-03-10
申请号：EP93113334.2
申请日：1993-08-20
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Cordoba, Michael V. , Hardee, Kim C. , Butler, Douglas B.
IPC分类号： G05F3/24
CPC分类号： G05F3/245 , G05F3/247 , Y10S323/907

2. 发明公开

EP0585755A1 Apparatus and method providing a MOS temperature compensated voltage reference for low voltages and wide voltage ranges 失效转让
标题翻译：装置和用于产生用于低电压和高的工作电压范围内的温度补偿的参考电压的方法。
公开(公告)号：EP0585755A1
公开(公告)日：1994-03-09
申请号：EP93113334.2
申请日：1993-08-20
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Cordoba, Michael V. , Hardee, Kim C. , Butler, Douglas B.
IPC分类号： G05F3/24
CPC分类号： G05F3/245 , G05F3/247 , Y10S323/907
摘要： A reference voltage generator which compensates for temperature and V CC variations includes a constant current source and a MOS P-channel transistor (28). The constant current source provides a constant current over a wide range of V CC that corresponds to biasing a p-channel transistor (28) in a region where its resistance is constant. The output of the current source is supplied to the P-channel transistor (28), which is in saturation. The constant current provides a constant voltage drop across the P-channel transistor (28). Hence, a stable reference voltage is generated. Temperature compensation is provided by biasing the P-channel transistor (28) to saturation and supplying a constant current that the corresponds to biasing a p-channel transistor (28) where the resistance is substantially constant over a temperature range. The current causes a voltage drop across the P-channel transistor (28) to maintain a stable reference voltage. Also, temperature compensation is further provided by utilizing the negative temperature coefficients of the resistors (14, 24) included in the constant current source.
摘要翻译：这对于温度变化和VCC补偿的基准电压发生器包括一个恒流源和一个MOS P沟道晶体管（28）。恒定电流源提供在宽范围的VCC的恒定电流确实对应于一个区域偏置p沟道晶体管（28），其中其阻值为常数。电流源的输出被供给到P沟道晶体管（28），所有这些都处于饱和状态。恒定电流提供横跨P沟道晶体管（28）的恒定的电压降。因此，产生稳定的参考电压。温度补偿是通过偏置P沟道晶体管（28）饱和，提供恒定电流提供，DASS模具对应于偏置p沟道晶体管（28），其中所述电阻的温度范围内基本上恒定。该电流导致跨P沟道晶体管（28）的电压降，以保持一个稳定的参考电压。所以，温度补偿是通过利用进一步（14，24）包括在恒定电流源中的电阻器的负温度系数设置。

3. 发明授权

EP0745998B1 Circuit and method for accessing memory cells of a memory device 失效
标题翻译：电路和方法，用于访问存储器阵列的存储单元
公开(公告)号：EP0745998B1
公开(公告)日：2004-01-02
申请号：EP95630105.5
申请日：1995-09-26
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Parris, Michael C. , Butler, Douglas B. , Hardee, Kim C.
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/46 , G11C8/12 , G11C29/34

4. 发明公开

EP0795894A2 Planarized integrated circuit product and method for making it 失效
标题翻译： Planarisierte integrierte Schaltung und Verfahren zur Herstellung derselben
公开(公告)号：EP0795894A2
公开(公告)日：1997-09-17
申请号：EP96630032.9
申请日：1996-05-15
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Butler, Douglas B.
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/82 , H01L27/088
CPC分类号： H01L21/31053 , H01L21/763
摘要： A planarized integrated circuit and method for making it are disclosed. The method includes forming portions of a transistor structure that extend to an elevation on an integrated circuit substrate above intermediate regions above the substrate. The portions have an oxide layer on their top surfaces. A layer of polysilicon is formed overall, including in the intermediate regions, to a depth in the intermediate regions larger than the elevation to which the portions of the transistor structure extend. A chemical-mechanical-polishing step is performed on the polysilicon overall to a depth at least extending to the oxide layer on the transistor portions to create a first planarized surface. In subsequent processing, a layer of oxide may be formed over the planarized surface, with source/drain extension regions patterned in the layer of oxide and underlying structures to the surface of the substrate. Source and drain region impurities are implanted for an MOS transistor in the source/drain extension regions, and a second layer of spacer oxide is formed overall. Portions of the spacer oxide are removed in bottom portions of the source/drain extension regions, and a layer of polysilicon is formed overall to a depth deeper than a depth of the source/drain extension regions. A chemical-mechanical-polishing step is performed on the polysilicon overall to a depth at least extending to the second layer of spacer oxide to create a second planarized surface.
摘要翻译：公开了一种平面化集成电路及其制造方法。该方法包括形成晶体管结构的部分，该晶体管结构在衬底上方的中间区域上延伸到集成电路衬底上的高度。这些部分在其顶表面上具有氧化物层。整体形成多晶硅层，其中包括在中间区域中的中间区域的深度大于晶体管结构的部分延伸的高度。在整体上对多晶硅进行化学机械抛光步骤，其深度至少延伸到晶体管部分上的氧化物层，以形成第一平坦化表面。在随后的处理中，可以在平坦化表面上形成一层氧化物，其中源极/漏极延伸区域在氧化物层和下面的结构层中图案化到衬底的表面。在源极/漏极延伸区域中注入源极和漏极区杂质用于MOS晶体管，并且整体形成第二层间隔氧化物层。间隔氧化物的一部分在源极/漏极延伸区域的底部被去除，并且多晶硅层整体形成到比源极/漏极延伸区域的深度更深的深度。在整体上对多晶硅进行化学机械抛光步骤，至少延伸至第二隔离层氧化层，以产生第二平坦化表面。

5. 发明公开

EP1001465A2 Multi-chip memory apparatus and associated method 审中-公开
标题翻译： Mehrchipspeicher und Herstellungsmethode
公开(公告)号：EP1001465A2
公开(公告)日：2000-05-17
申请号：EP99308443.3
申请日：1999-10-26
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Butler, Douglas B.
IPC分类号： H01L25/065
CPC分类号： H01L25/18 , H01L23/49575 , H01L24/48 , H01L25/0657 , H01L2224/05599 , H01L2224/16145 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/85399 , H01L2225/0651 , H01L2225/06513 , H01L2225/06582 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012 , H01L2224/45099
摘要： A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.
摘要翻译：多芯片集成电路及相关方法相对于由接合线形成的常规连接，提供了显着降低的电容和电感水平的接口。集成电路的芯片之一包括诸如DRAM的存储器件，并且集成电路的另一芯片由诸如CPU或图形控制器的逻辑芯片形成。利用片上芯片技术将存储芯片安装在逻辑芯片上。由于将芯片连接在一起的接口的电容和电感水平降低，所得到的集成电路可以以增加的速度和降低的功耗水平来操作。

6. 发明公开

EP0745998A1 Circuit and method for accessing memory cells of a memory device 失效
标题翻译： Schaltung und Verfahren zum Zugriff auf Speicherzellen einer Speicheranordnung
公开(公告)号：EP0745998A1
公开(公告)日：1996-12-04
申请号：EP95630105.5
申请日：1995-09-26
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Parris, Michael C. , Butler, Douglas B. , Hardee, Kim C.
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/46 , G11C8/12 , G11C29/34
摘要： A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.
摘要翻译：一种用于同时寻址存储器件的存储器阵列的至少两行存储器单元的电路和方法。在老化期间在存储器件测试期间同时寻址至少两行存储器单元，可以在缩短的时间周期内对存储器件进行测试。

7. 发明公开

EP0788164A1 Memory cell configuration for increased capacitor area 失效
标题翻译： SpeicherzellenanordnungfürerhöhteKondensatoroberfläche
公开(公告)号：EP0788164A1
公开(公告)日：1997-08-06
申请号：EP96630046.9
申请日：1996-08-12
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Butler, Douglas B.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A capacitor for use as a part of a memory cell, such as a DRAM, constructed according to design rules of 0.4µm, or less. The capacitor includes a cross-shaped capacitor electrode (50) connected to a memory transistor of the DRAM and may overlie bit lines (57) of the DRAM to provide a COB array. An insulation layer (52) overlies the memory transistor (56), and the cross-shaped capacitor electrode (50) in turn overlies the insulation layer. A dielectric layer (62) and a conformal capacitor electrode (60) are arranged with respect to the cross-shaped capacitor electrode to complete the capacitor. The cross-shaped capacitor electrode may be dimensioned to be about 0.2µm, or more, thick, 1.6µm long, 1.6µm wide, with each arm of the cross-shaped electrode about 0.4µm wide, wherein the lateral sides of the electrode contribute to a surface area of the capacitor electrode to increase the capacitance of the capacitor in which it is included.
摘要翻译：用作根据设计规则构建的存储单元（诸如DRAM）的一部分的电容器，小于或等于0.4μm。电容器包括连接到DRAM的存储晶体管的十字形电容器电极（50），并且可以覆盖DRAM的位线（57）以提供COB阵列。绝缘层（52）覆盖存储晶体管（56），十字形电容器电极（50）又覆盖绝缘层。相对于十字形电容器电极布置介质层（62）和保形电容电极（60）以完成电容器。十字形电容器电极的尺寸可以是大约0.2μm或更厚，1.6μm长，1.6μm宽，十字形电极的每个臂宽度大约为0.4μm，其中侧面的电极有助于电容器电极的表面积，以增加其中包括的电容器的电容。

8. 发明公开

EP0697757A1 Electrostatic discharge protection circuit for an integrated circuit device 无效
标题翻译： Elektrostatische Entladungsschutzschaltungfürintegrierte Schaltungsanordnung
公开(公告)号：EP0697757A1
公开(公告)日：1996-02-21
申请号：EP94630054.8
申请日：1994-09-15
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Butler, Douglas B. , Faue, Jon A.
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit for an integrated circuit is formed by a shunt transistor (62) selectively coupling the V CC and V SS input pins, or other relatively high capacitance IC circuit nodes. A capacitor (70) couples the V CC pin to the transistor gate to turn it on and thereby shunt the ESD current through the transistor to V SS . A resistor (72) couples the V SS pin to the transistor gate to cause the transistor to turn off after the current has been discharged therethrough. The values for the capacitor and resistor are chosen to provide a resultant time constant which is long relative to a Human Body Model ESD test circuit and short relative to typical voltage rise times encountered at the protected circuit nodes.
摘要翻译：用于集成电路的ESD保护电路由选择性地耦合VCC和VSS输入引脚或其他相对高电容的IC电路节点的并联晶体管（62）形成。电容器（70）将VCC引脚耦合到晶体管栅极以将其导通，从而将通过晶体管的ESD电流分流到VSS。电阻器（72）将VSS引脚耦合到晶体管栅极，以在电流从其中排出之后使晶体管截止。选择电容器和电阻器的值以提供相对于人体模型ESD测试电路长的相对时间常数，并且相对于受保护电路节点处遇到的典型电压上升时间短。

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