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1. 发明公开

EP0750310A1 High speed differential current sense amplifier with positive feedback 失效
标题翻译： Hochgeschwindigkeitsdifferentialstromleseverstärkermit positienRückmeldung
公开(公告)号：EP0750310A1
公开(公告)日：1996-12-27
申请号：EP95109683.3
申请日：1995-06-22
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corporation
发明人： Faue, Jon Allan
IPC分类号： G11C7/06
CPC分类号： H03K3/012 , G11C7/062 , G11C7/065 , G11C2207/063
摘要： Positive feedback increases switching speeds and negative feedback prevents the voltage at the inputs (12, 14) from varying too far in a sense amplifier (20) used to sense voltage differentials on bit lines or data lines of semiconductor memories, or elsewhere. Switching speeds improve without increased current consumption.
摘要翻译：正反馈增加了开关速度和负反馈，防止在用于感测半导体存储器或其他地方的位线或数据线上的电压差的读出放大器（20）中输入端（12,14）处的电压变化太远。切换速度提高而不增加电流消耗。

2. 发明公开

EP0948136A2 Apparatus, and associated method, for preventing occurence of latch-up in an electronic circuit 审中-公开
标题翻译：设备和相关联的方法用于避免在电子电路中的情况下，锁定
公开(公告)号：EP0948136A2
公开(公告)日：1999-10-06
申请号：EP99630028.1
申请日：1999-03-26
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Faue, Jon Allan
IPC分类号： H03K17/22 , H03K19/0185
CPC分类号： H03K3/356147 , H03K17/223
摘要： A latch-up protector, and an associated method, for an electronic circuit powered by both a fixed power supply and a pumped power supply. Operation of the latch-up protector prevents the occurrence of latch-up of the circuit during powering-up of the circuit. During powering-up of the electronic circuit, the latch-up protector prevents the application of an input signal to the electronic circuit which might instigate the occurrence of latch-up until the pumped power supply reaches a selected voltage level.
摘要翻译：闩锁保护装置，以及相关的方法，在搭载两个固定电源和一个泵送电源电子电路。闩锁保护装置的动作防止电路的加电期间的电路的闩锁发生。在电子电路的加电，闩锁保护防止将输入信号的给，直到泵送电源达到选定的电压级可能煽动的闩锁发生的电子电路中的应用。

3. 发明公开

EP0869419A2 Fast voltage regulation without overshoot 失效
标题翻译： Schnelle Spannungsregelung ohneÜberspannung
公开(公告)号：EP0869419A2
公开(公告)日：1998-10-07
申请号：EP97630070.7
申请日：1997-10-17
申请人： Nippon Steel Semiconductor Corp. , UNITED MEMORIES, INC.
发明人： Tiede, John William , Faue, Jon Allan
IPC分类号： G05F1/46
CPC分类号： G05F1/465
摘要： An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.
摘要翻译：一种片上稳压器，用于控制具有耦合以接收外部电源电压的第一端子的稳压晶体管的栅极，以及耦合到对芯片上形成的内部电路提供调节的电压电平的第二端子，形成片式稳压器。片上稳压器包括用于检测何时连接稳压晶体管的第二端的高电流负载被激活的电路。提供控制晶体管，其具有耦合以接收外部电源电压的第一端子，耦合到调节器晶体管的栅极的第二端子和响应于用于检测的装置的栅极。在操作中，响应于高电流负载的激活，在调节器晶体管的栅极上产生具有预选持续时间的过冲部分的控制电压。

4. 发明公开

EP0990974A2 Synchronous integrated circuit device utilizing an integrated clock/command technique 审中-公开
标题翻译：同步整合器（Schaltungsvorrichtung mit integrierter）Takt / Befehl Verfahren
公开(公告)号：EP0990974A2
公开(公告)日：2000-04-05
申请号：EP99307628.0
申请日：1999-09-28
申请人： UNITED MEMORIES, INC. , Nippon Steel Semiconductor Corp.
发明人： Faue, Jon Allan
IPC分类号： G06F1/10
CPC分类号： G06F1/10
摘要： A technique for integrating an internal clock signal with various function commands in an integrated circuit device having an externally supplied clock signal to create a set of command clocks which have the same rising (or falling) edge time, duty cycle and duration and are, therefore, inherently clocked to ameliorate signal "race" and "skew" conditions encountered in prior designs. The technique of the present invention, therefore, improves overall device operational speeds in executing commands by reducing internal gate delays and resulting in faster data access times in integrated circuit memory devices such as synchronous dynamic random access memory ("SDRAM") devices. Moreover, because the resultant design provides faster operation times, lower cost process technologies may be utilized to achieve substantially comparable performance levels.
摘要翻译：在具有外部提供的时钟信号的集成电路器件中集成内部时钟信号与各种功能命令的技术，以产生具有相同上升（或下降）边沿时间，占空比和持续时间的一组命令时钟，因此，固有地改善了以前的设计中遇到的信号“种族”和“歪斜”状况。因此，本发明的技术通过减少内部门延迟并导致诸如同步动态随机存取存储器（“SDRAM”）装置的集成电路存储器件中的数据访问时间更快地提高了执行命令的整体设备操作速度。此外，由于所得到的设计提供更快的操作时间，所以可以利用较低成本的处理技术来实现基本可比的性能水平。

5. 发明公开

EP0869617A1 Pad input select circuit for use with bond options 失效
标题翻译： Eingangswahlschaltung zur Anwendung mit Bonddraht-Konfiguration
公开(公告)号：EP0869617A1
公开(公告)日：1998-10-07
申请号：EP97630071.5
申请日：1997-10-17
申请人： Nippon Steel Semiconductor Corp. , UNITED MEMORIES, INC.
发明人： Tiede, John William , Faue, Jon Allan
IPC分类号： H03K19/173 , G11C7/00
CPC分类号： H03K19/173 , G11C7/1045
摘要： A configurable input device for an integrated circuit having a plurality of input pads, the input device including a plurality of buffers, where each buffer is associated with one of the input pads. Each buffer receives a mode select signal and the buffer is responsive to the mode select signal to place the buffer in an enabled mode or a disabled mode. A receiver portion within each buffer is coupled to the associated input pad. The receiver portion pulls the associated input pad to a preselected logic state while the buffer is in the disabled mode. An output driver within each buffer generates an output signal responsive to a signal on the associated input pad while the buffer is in the enable mode and provides a high impedance while the buffer is in the disabled mode. An output node is coupled to the output drivers of the plurality of buffers.
摘要翻译：一种用于具有多个输入焊盘的集成电路的可配置输入装置，所述输入装置包括多个缓冲器，其中每个缓冲器与所述输入焊盘中的一个相关联。每个缓冲器接收模式选择信号，并且缓冲器响应于模式选择信号以将缓冲器置于使能模式或禁用模式。每个缓冲器内的接收器部分耦合到相关的输入焊盘。当缓冲器处于禁用模式时，接收器部分将相关联的输入焊盘拉到预选逻辑状态。每个缓冲器中的输出驱动器响应于相关输入焊盘上的信号而产生输出信号，同时缓冲器处于使能模式，并且当缓冲器处于禁用模式时提供高阻抗。输出节点耦合到多个缓冲器的输出驱动器。

6. 发明公开

EP0869419A3 Fast voltage regulation without overshoot 失效
标题翻译：没有过压快速电压控制
公开(公告)号：EP0869419A3
公开(公告)日：1999-04-14
申请号：EP97630070.7
申请日：1997-10-17
申请人： Nippon Steel Semiconductor Corp. , UNITED MEMORIES, INC.
发明人： Tiede, John William , Faue, Jon Allan
IPC分类号： G05F1/46
CPC分类号： G05F1/465
摘要： An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.

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