专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08325127B2 Shift register and architecture of same on a display panel 有权
标题翻译：移位寄存器和结构在显示面板上
公开(公告)号：US08325127B2
公开(公告)日：2012-12-04
申请号：US12823237
申请日：2010-06-25
申请人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/287 , G09G3/20 , G09G3/3677 , G09G2310/0205 , G09G2310/0281 , G09G2310/0286 , G09G2310/0297 , G09G2310/06
摘要： The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.
摘要翻译：本发明涉及一种显示面板中的移位寄存器和GOA结构，包括基板和空间上形成在衬底上的多个像素，其限定多个像素行，每个像素行具有高度H.移位寄存器具有多个移位寄存器级，以这样的方式在基板上空间和顺序地布置，使得每个移位寄存器级的布局具有（j * H）的高度，j是大于1的整数。每个移位寄存器级被配置为分别产生用于驱动j个相邻像素行的j个扫描信号。

22. 发明申请

US20110316833A1 Shift Register and Architecture of Same on a Display Panel 有权
标题翻译：移位寄存器和显示面板上的相同结构
公开(公告)号：US20110316833A1
公开(公告)日：2011-12-29
申请号：US12823237
申请日：2010-06-25
申请人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Chun-Huan Chang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/287 , G09G3/20 , G09G3/3677 , G09G2310/0205 , G09G2310/0281 , G09G2310/0286 , G09G2310/0297 , G09G2310/06
摘要： The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.
摘要翻译：本发明涉及一种显示面板中的移位寄存器和GOA结构，包括基板和空间上形成在衬底上的多个像素，其限定多个像素行，每个像素行具有高度H.移位寄存器具有多个移位寄存器级，以这样的方式在基板上空间和顺序地布置，使得每个移位寄存器级的布局具有（j * H）的高度，j是大于1的整数。每个移位寄存器级被配置为分别产生用于驱动j个相邻像素行的j个扫描信号。

23. 发明授权

US08456454B2 Display panel 有权
标题翻译：显示面板
公开(公告)号：US08456454B2
公开(公告)日：2013-06-04
申请号：US12488946
申请日：2009-06-22
申请人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
发明人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
IPC分类号： G06F3/038 , G09G5/00 , G02F1/1333
CPC分类号： G09G3/3677 , G09G2300/0426 , G09G2330/08 , G09G2330/12
摘要： A display panel is disclosed, which includes a substrate, a shift register array, plural scan lines, a compensating circuit, a first repair line, and a second repair line. The shift register array having plural shift registers is disposed on a non-display area of the substrate. The scan lines connect to the shift registers respectively to drive plural display units. The first repair line and the second repair line are connected to the compensating circuit and bridged over two ends of each scan line in the non-display area, respectively.
摘要翻译：公开了一种显示面板，其包括基板，移位寄存器阵列，多条扫描线，补偿电路，第一修复线和第二修复线。具有多个移位寄存器的移位寄存器阵列设置在基板的非显示区域上。扫描线分别连接到移位寄存器以驱动多个显示单元。第一修理线和第二修复线分别连接到补偿电路并桥接在非显示区域中的每条扫描线的两端。

24. 发明授权

US08175215B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08175215B2
公开(公告)日：2012-05-08
申请号：US12572247
申请日：2009-10-01
申请人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
发明人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.
摘要翻译：移位寄存器包括多个级联连接级。每一级响应于时钟信号和第一控制信号产生输出信号。每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。上拉模块用于根据时钟信号提供输出信号。上拉驱动模块响应于第一控制信号而导通上拉模块。第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

25. 发明授权

US08027426B1 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08027426B1
公开(公告)日：2011-09-27
申请号：US12837244
申请日：2010-07-15
申请人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G2310/0286 , G11C19/184
摘要： An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.
摘要翻译：示例性移位寄存器包括多个晶体管。对晶体管进行起始脉冲信号，第一时钟信号和第二时钟信号的控制，以产生栅极驱动信号。第一时钟信号和第二时钟信号相对于彼此相位反相。第一时钟信号的逻辑低电平和第二时钟信号的另一个逻辑低电平彼此不同。而且，晶体管是负阈值电压晶体管。在晶体管处于截止状态的情况下，每个晶体管的栅极处的电位低于晶体管的源极/漏极处的另一个电位。

26. 发明申请

US20110002437A1 SHIFT REGISTERS 有权
标题翻译：移位寄存器
公开(公告)号：US20110002437A1
公开(公告)日：2011-01-06
申请号：US12607156
申请日：2009-10-28
申请人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
发明人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal.
摘要翻译：提供一个移位寄存器，包括一个第一移位寄存单元和一个第二移位寄存单元。第一移位寄存单元在第一输出端产生第一触发信号，并包括第一下拉电路。第二移位寄存单元接收第一触发信号并在第二输出端产生第二触发信号。第一触发信号和第二触发信号被依次断言。第二移位登记单元包括第二下拉电路。第一下拉电路和第二下拉电路在不同时间执行下拉操作。当第一下拉电路不执行下拉操作时，第二下拉电路对第一输出端子执行下拉操作。

27. 发明授权

US08502948B2 Active device array substrate 有权
标题翻译：有源器件阵列衬底
公开(公告)号：US08502948B2
公开(公告)日：2013-08-06
申请号：US12858433
申请日：2010-08-17
申请人： Kuo-Chang Su , Kuo-Hua Hsu , Chun-Hsin Liu , Yung-Chih Chen
发明人： Kuo-Chang Su , Kuo-Hua Hsu , Chun-Hsin Liu , Yung-Chih Chen
IPC分类号： G02F1/1343
CPC分类号： G02F1/136286 , G09G3/3614 , G09G3/3648 , G09G2300/0426 , G09G2300/0452 , G09G2320/0233 , G09G2330/021
摘要： An active device array substrate includes a substrate, first scan lines, second scan lines, data lines, and pixels. The first and the second scan lines are alternately arranged along a first direction. The data lines are arranged in parallel along a second direction. The pixels are arranged to form first pixel rows and second pixel rows alternately arranged in the first direction. The first pixel row includes first and second pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The second pixel row includes third and fourth pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The pixels between two adjacent data lines are arranged in two columns. Among the pixels in the same column, the pixels in odd rows and in even rows are electrically connected to different data lines, respectively.
摘要翻译：有源器件阵列衬底包括衬底，第一扫描线，第二扫描线，数据线和像素。第一和第二扫描线沿着第一方向交替排列。数据线沿第二方向平行布置。像素被布置成形成沿第一方向交替布置的第一像素行和第二像素行。第一像素行包括分别电连接到第一扫描线，第二扫描线和数据线的第一和第二像素。第二像素行包括分别电连接到第一扫描线，第二扫描线和数据线的第三和第四像素。两个相邻数据线之间的像素排列成两列。在同一列中的像素中，奇数行和偶数行中的像素分别电连接到不同的数据线。

28. 发明申请

US20120169679A1 LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：液晶显示装置
公开(公告)号：US20120169679A1
公开(公告)日：2012-07-05
申请号：US13316572
申请日：2011-12-12
申请人： Chih-Ying Lin , Chun-Hsin Liu , Kuo-Chang Su , Yung-Chih Chen
发明人： Chih-Ying Lin , Chun-Hsin Liu , Kuo-Chang Su , Yung-Chih Chen
IPC分类号： G09G3/36 , G06F3/038
CPC分类号： G09G3/3688 , G02F1/13624
摘要： A liquid crystal display device includes a plurality of pixel driving circuits and a pixel array. Each pixel driving circuit of the plurality of pixel driving circuits includes four thin film transistors and has four output terminals, where each thin film transistor is used for driving an output terminal of the four output terminals, and the four output terminals are coupled to two gate lines and two sharing lines respectively for outputting two main output signals and two sharing output signals. The phases and timings of the two main output signals and the two sharing output signals are all the same. A pixel of the pixel array is charged/discharged to a specific voltage level according to a main output signal of the two main output signals, a sharing output signal, and a signal of a data line.
摘要翻译：液晶显示装置包括多个像素驱动电路和像素阵列。多个像素驱动电路的每个像素驱动电路包括四个薄膜晶体管，并且具有四个输出端子，其中每个薄膜晶体管用于驱动四个输出端子的输出端子，并且四个输出端子耦合到两个栅极线路和两条共用线路分别输出两路主输出信号和两路共享输出信号。两个主输出信号和两个共享输出信号的相位和时序都相同。像素阵列的像素根据两个主输出信号的主输出信号，共享输出信号和数据线的信号而被充/放电到特定电压电平。

29. 发明授权

US08139708B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08139708B2
公开(公告)日：2012-03-20
申请号：US13175475
申请日：2011-07-01
申请人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G2310/0286 , G11C19/184
摘要： An exemplary shift register includes a control circuit and an output circuit. The control circuit is electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal. A logic low level of the first clock pulse signal is lower than a level of the power supply voltage. The output circuit is subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal. The second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.
摘要翻译：示例性移位寄存器包括控制电路和输出电路。控制电路电耦合以接收起始脉冲信号，第一时钟脉冲信号和电源电压，并且用于根据起始脉冲信号和第一时钟脉冲信号产生使能信号。第一时钟脉冲信号的逻辑低电平低于电源电压的电平。对输出电路进行使能信号的控制，并根据第二时钟脉冲信号产生栅极驱动信号。第二时钟脉冲信号和第一时钟脉冲信号相对于彼此相位反转，并且第二时钟脉冲信号的逻辑低电平高于电源电压的电平。

30. 发明申请

US20110228891A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20110228891A1
公开(公告)日：2011-09-22
申请号：US12837244
申请日：2010-07-15
申请人： Yu-Chung YANG , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Yu-Chung YANG , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/28
CPC分类号： G11C19/28 , G09G2310/0286 , G11C19/184
摘要： An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.
摘要翻译：示例性移位寄存器包括多个晶体管。对晶体管进行起始脉冲信号，第一时钟信号和第二时钟信号的控制，以产生栅极驱动信号。第一时钟信号和第二时钟信号相对于彼此相位反相。第一时钟信号的逻辑低电平和第二时钟信号的另一个逻辑低电平彼此不同。此外，晶体管是负阈值电压晶体管。在晶体管处于截止状态的情况下，每个晶体管的栅极处的电位低于晶体管的源极/漏极处的另一个电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式