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21. 发明申请

US20110157082A1 Matrix Resistive Touch Panel and Design Method Thereof 审中-公开
标题翻译：矩阵电阻式触摸屏及其设计方法
公开(公告)号：US20110157082A1
公开(公告)日：2011-06-30
申请号：US12978789
申请日：2010-12-27
申请人： Yung-Chang Lin , Ming-Chuan Lin , Lin Lin , Chih-Chiang Lin
发明人： Yung-Chang Lin , Ming-Chuan Lin , Lin Lin , Chih-Chiang Lin
IPC分类号： G06F3/045
CPC分类号： G06F3/045
摘要： A matrix resistive touch panel including a plurality of first sensing electrodes, a plurality of second sensing electrodes, a control circuit and a compensating circuit is provided. Each first sensing electrode has a first end and a second end. Each second sensing electrode has a third end and a fourth end. The compensating circuit is electrically connected to the control circuit, the first and the second ends of the first sensing electrodes, and the third and the fourth ends of the second sensing electrodes. The compensating circuit is used for equating a plurality of first impedances between the first ends and the control circuit, equating a plurality of second impedances between the second ends and the control circuit, equating a plurality of third impedances between the third ends and the control circuit, and equating a plurality of fourth impedances between the fourth ends and the control circuit.
摘要翻译：提供了包括多个第一感测电极，多个第二感测电极，控制电路和补偿电路的矩阵电阻式触摸面板。每个第一感测电极具有第一端和第二端。每个第二感测电极具有第三端和第四端。补偿电路电连接到控制电路，第一感测电极的第一端和第二端以及第二感测电极的第三端和第四端。补偿电路用于将第一端和控制电路之间的多个第一阻抗相等，将第二端与控制电路之间的多个第二阻抗相等，将第三端之间的多个第三阻抗与控制电路并且将第四端之间的多个第四阻抗与控制电路相等。

22. 发明授权

US07351634B2 Trench-capacitor DRAM device and manufacture method thereof 有权
标题翻译：沟槽电容器DRAM器件及其制造方法
公开(公告)号：US07351634B2
公开(公告)日：2008-04-01
申请号：US11420222
申请日：2006-05-25
申请人： Yi-Nan Su , Yung-Chang Lin , Jun-Chi Huang
发明人： Yi-Nan Su , Yung-Chang Lin , Jun-Chi Huang
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.
摘要翻译：公开了一种制造沟槽电容器的方法。提供具有第一焊盘层的衬底。 STI结构嵌入到第一焊盘层和衬底中。在第一焊盘层和STI结构上沉积第二焊盘层。两个相邻的沟槽被蚀刻到第一，第二焊盘层和半导体衬底中。蚀刻第二焊盘层和两个沟槽之间的STI结构的一部分以形成脊。衬套形成在沟槽的内表面上。在衬套上形成第一多晶硅层。在第一多晶硅层上形成电容器电介质层。两个相邻的沟槽被填充有第二多晶硅层。然后蚀刻第二多晶硅层直到暴露电容器介电层。制造工艺易于集成到SoC芯片。

23. 发明申请

US20070238244A1 TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： TRENCH-CAPACITOR DRAM器件及其制造方法
公开(公告)号：US20070238244A1
公开(公告)日：2007-10-11
申请号：US11279254
申请日：2006-04-11
申请人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
发明人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
摘要翻译：沟槽电容器结构包括其上包括STI结构的半导体衬底。电容器深沟槽被蚀刻到半导体衬底中。环状氧化物层设置在电容器深沟槽的内表面上。第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。在第一掺杂多晶硅层上形成电容器电介质层。第二掺杂多晶硅层形成在电容器介电层上。在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。

24. 发明授权

US06683342B2 Memory structure and method for manufacturing the same 有权
标题翻译：内存结构及其制造方法
公开(公告)号：US06683342B2
公开(公告)日：2004-01-27
申请号：US10177599
申请日：2002-06-19
申请人： Yung-Chang Lin
发明人： Yung-Chang Lin
IPC分类号： H01L2976
CPC分类号： H01L27/10894 , H01L21/823425 , H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/10888
摘要： A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the periphery device of an embedded memory structure, and the second gate structure will become the memory device of the embedded memory structure. A first spacer and a second spacer are fabricated on the sidewalls of the first gate structure and the second gate structure. After the formation of the contacts between the second gate structures, the second spacer on the sidewall of the second gate structure will be removed. Therefore, there is the dual spacer, including the first spacer and the second spacer, on the sidewall of the first gate structure. In the other hand, the single spacer, only the first spacer included, is left on the sidewall of the second gate structure. Therefore, this invention can fabricate the spacers in different scale based on the requirement of the semiconductor manufacture for the periphery device and the memory device.
摘要翻译：在本发明中公开了一种记忆结构及其制造方法。第一栅极结构和第二栅极结构设置在基板上。在植入过程之后，第一栅极结构将成为嵌入式存储器结构的周边器件，并且第二栅极结构将成为嵌入式存储器结构的存储器件。在第一栅极结构和第二栅极结构的侧壁上制造第一间隔物和第二间隔物。在形成第二栅极结构之间的接触之后，将去除第二栅极结构的侧壁上的第二间隔物。因此，在第一栅极结构的侧壁上存在包括第一间隔物和第二间隔物的双间隔物。另一方面，单个间隔物仅包括第一间隔物留在第二栅极结构的侧壁上。因此，本发明可以根据外围装置和存储装置的半导体制造的要求，制造不同规模的间隔物。

25. 发明授权

US06238958B1 Method for forming a transistor with reduced source/drain series resistance 失效
标题翻译：用于形成具有降低的源极/漏极串联电阻的晶体管的方法
公开(公告)号：US06238958B1
公开(公告)日：2001-05-29
申请号：US09477109
申请日：1999-12-31
申请人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
发明人： Kirk Hsu , Yung-Chang Lin , Wen-Jeng Lin
IPC分类号： H01L2184
CPC分类号： H01L29/665 , H01L29/41775 , H01L29/41783
摘要： A method for forming a transistor in integrated circuits is disclosed. The method includes the following steps. A substrate is first provided. An insulating layer is then formed on the substrate. A conductor layer is formed on the insulating layer. Subsequently, a patterned photoresist layer is formed on the conductor layer. Next, an etch process is used to etch the conductor layer which has a sidewall. The patterned photoresist layer is then removed. After forming a liner layer on the sidewall of the conductor layer, a lightly doped drain is formed on and in the substrate. Then, a spacer is formed on the liner layer. Thereafter, a proper process is used to introduce ions into the lightly doped drain, and then a source/drain region is completed. The steps with follow include annealing the source/drain region and removing the spacer. Subsequently, an epi-silicon layer is formed on the lightly doped drain region, the source/drain region and the top surface of the conductor layer. Finally, the epi-silicon layer is treated with a salicidation process to form a salicide layer.
摘要翻译：公开了一种在集成电路中形成晶体管的方法。该方法包括以下步骤。首先提供基板。然后在衬底上形成绝缘层。在绝缘层上形成导体层。随后，在导体层上形成图案化的光致抗蚀剂层。接下来，使用蚀刻工艺来蚀刻具有侧壁的导体层。然后去除图案化的光致抗蚀剂层。在导体层的侧壁上形成衬垫层之后，在衬底上和衬底中形成轻掺杂漏极。然后，在衬垫层上形成间隔物。此后，使用适当的方法将离子引入轻掺杂的漏极中，然后完成源极/漏极区域。随后的步骤包括对源极/漏极区进行退火并去除间隔物。随后，在轻掺杂漏区，导体层的源/漏区和顶表面上形成外延硅层。最后，用硅化物处理外延硅层以形成自对准硅层。

26. 发明授权

US06187674B1 Manufacturing method capable of preventing corrosion and contamination of MOS gate 失效
标题翻译：能够防止MOS栅的腐蚀和污染的制造方法
公开(公告)号：US06187674B1
公开(公告)日：2001-02-13
申请号：US09208605
申请日：1998-12-08
申请人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L2144
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L29/4941
摘要： A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.
摘要翻译： MOS门制造操作能够防止酸腐蚀和车站污染。该制造方法包括以下步骤：在硅衬底上顺序地形成多晶硅层，阻挡层，硅化物层和覆盖层，然后蚀刻以形成栅极结构。接下来，进行快速热处理以在阻挡层的暴露的侧壁上形成氧化物层。最后，通过在栅极的每一侧上形成具有轻掺杂漏极结构的源极/漏极区域来清洁衬底。薄氧化物层能够保护阻挡层免受酸腐蚀，而不会导致栅极导电性的任何明显增加。

27. 发明授权

US09335841B2 Computer readable media can perform interference image determining method and interference image determining apparatus 有权
标题翻译：计算机可读介质可以执行干扰图像确定方法和干涉图像确定装置
公开(公告)号：US09335841B2
公开(公告)日：2016-05-10
申请号：US13562285
申请日：2012-07-30
申请人： Hsin-Chia Chen , Yen-Min Chang , Yu-Hao Huang , Wen-Han Yao , Ching-Lin Chung , Yung-Chang Lin , Tsung-Fa Wang , Ming-Tsan Kao
发明人： Hsin-Chia Chen , Yen-Min Chang , Yu-Hao Huang , Wen-Han Yao , Ching-Lin Chung , Yung-Chang Lin , Tsung-Fa Wang , Ming-Tsan Kao
IPC分类号： G06K9/00 , G06F3/0354 , G06F3/042
CPC分类号： G06F3/03547 , G06F3/042 , G06F2203/0338
摘要： A computer readable media having at least one program code recorded thereon. An interference image determining method can be performed when the program code is read and executed. The interference image determining method comprises: (a) controlling a light source to illuminate an object on a detecting surface to generate an image; (b) controlling a sensor to catch a current frame of the image; (c) utilizing an image characteristic included in the current frame to determine a interference image part of the current frame; and (d) updating a defined interference image according to the determined interference image part.
摘要翻译：一种其上记录有至少一个程序代码的计算机可读介质。当读取和执行程序代码时，可以执行干涉图像确定方法。干扰图像确定方法包括：（a）控制光源照射检测表面上的物体以产生图像; （b）控制传感器以捕获图像的当前帧; （c）利用包括在当前帧中的图像特性来确定当前帧的干扰图像部分; 以及（d）根据确定的干涉图像部分更新所定义的干涉图像。

28. 发明授权

US08664062B2 Method of manufacturing flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US08664062B2
公开(公告)日：2014-03-04
申请号：US13047758
申请日：2011-03-14
申请人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
发明人： Yung-Chang Lin , Nan-Ray Wu , Le-Tien Jung
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/76
CPC分类号： H01L27/11524 , H01L21/28273 , H01L27/11526 , H01L27/11536 , H01L27/1157 , H01L29/4983 , H01L29/512 , H01L29/6659 , H01L29/7833 , H01L29/7881
摘要： A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.
摘要翻译：制造闪速存储单元的方法包括提供其上形成有第一介电层的基板，在第一介电层上形成控制栅极，在控制栅极的侧壁上形成氧化物 - 氧化物（ONO）间隔物，形成在ONO间隔物两侧的衬底上的第二电介质层，并分别在第二电介质层上的ONO间隔物的外侧形成浮栅。

29. 发明申请

US20130243969A1 CHEMICAL VAPOR DEPOSITION OF GRAPHENE ON DIELECTRICS 有权
标题翻译：石墨化学蒸气沉积在电介质上
公开(公告)号：US20130243969A1
公开(公告)日：2013-09-19
申请号：US13592957
申请日：2012-08-23
申请人： Po-Yuan TENG , Yung-Chang Lin , Po-Wen Chiu
发明人： Po-Yuan TENG , Yung-Chang Lin , Po-Wen Chiu
IPC分类号： C23C16/26 , C23C16/02 , B82Y40/00
CPC分类号： C23C16/02 , B82Y30/00 , B82Y40/00 , C01B32/186 , C23C16/26
摘要： A method for synthesizing graphene films is disclosed. Monolayer or multilayer graphene can be directly grown on the dielectric materials. The method includes the following steps: disposing dielectric materials and metals in a reactor, introducing reaction gases into the reactor and decomposing the reaction gases by heating, thus directly depositing graphene films on the surfaces of the dielectrics. High crystalline quality and low-defect graphene films can be synthesized directly on dielectric materials, without the process of wet etching and transfer. The method opens up a more direct route to apply graphene on electronics, optoelectronics, and bio-medical devices.
摘要翻译：公开了一种用于合成石墨烯薄膜的方法。单层或多层石墨烯可直接生长在电介质材料上。该方法包括以下步骤：将电介质材料和金属放置在反应器中，将反应气体引入反应器并通过加热分解反应气体，从而在电介质的表面上直接沉积石墨烯膜。可以直接在电介质材料上合成高结晶质量和低缺陷石墨烯膜，无需湿蚀刻和转印。该方法开辟了一条更直接的途径，将石墨烯应用于电子，光电子和生物医疗设备。

30. 发明申请

US20120287976A1 NETWORK DEVICE RELATING TO DIGITAL SUBSCRIBER LINE 有权
标题翻译：与数字用户线相关的网络设备
公开(公告)号：US20120287976A1
公开(公告)日：2012-11-15
申请号：US13106885
申请日：2011-05-13
申请人： Yu-Sung Cho , Yung-Chang Lin
发明人： Yu-Sung Cho , Yung-Chang Lin
IPC分类号： H04B1/38
CPC分类号： H04L25/0264 , H04M11/062
摘要： A network device relating to a digital subscriber line (DSL) such as an asymmetrical DSL (ADSL) or a very high bit rate DSL (VDSL) is provided. In the present invention, the capacitors equipped into the network device are separated and grouped into two independent groups. When the network device runs out of power, the energy of one of the two independent groups is provided for generating the dying gasp signal, and the energy of the other of the two independent groups is provided for amplifying and transmitting the dying gasp signal to a Central Office (CO). Accordingly, the CO can be accurately known whether the network device runs out of power or not, and the respective capacitances of the two independent groups can be significantly reduced so as to reduce the cost of the network device.
摘要翻译：提供了与诸如不对称DSL（ADSL）或非常高比特率DSL（VDSL）的数字用户线（DSL）有关的网络设备。在本发明中，配置在网络装置中的电容器被分离并分组成两个独立的组。当网络设备耗尽电力时，提供两个独立组中的一个的能量用于产生垂死的气体信号，并且提供两个独立组中的另一个的能量用于放大并将垂直气体信号传输到中央办公室（CO）。因此，可以准确地知道CO网络设备是否断电，并且可以显着地减少两个独立组的各自的电容，从而降低网络设备的成本。

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