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21. 发明授权

US06993691B2 Series connected TC unit type ferroelectric RAM and test method thereof 失效
公开(公告)号：US06993691B2
公开(公告)日：2006-01-31
申请号：US10120146
申请日：2002-04-11
申请人： Ryu Ogiwara , Daisaburo Takashima , Yukihito Oowaki , Katsuhiko Hoya , Takeshi Watanabe
发明人： Ryu Ogiwara , Daisaburo Takashima , Yukihito Oowaki , Katsuhiko Hoya , Takeshi Watanabe
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C11/22
摘要： Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

22. 发明授权

US06906944B2 Ferroelectric memory 失效
标题翻译：铁电存储器
公开(公告)号：US06906944B2
公开(公告)日：2005-06-14
申请号：US10676004
申请日：2003-10-02
申请人： Yoshiaki Takeuchi , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Yukihito Oowaki
IPC分类号： G11C14/00 , G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.
摘要翻译：铁电存储器具有具有铁电电容器的存储单元阵列，其被分成多个块，设置在存储单元阵列的每个块中的升压功率电路，以产生存储器的操作所需的升压电压，升压电源开关，其设置在连接到外部电源端子的电力线与每个升压电力电路的电源端子之间，并且在正常操作期间保持ON;电压检测器电路，用于检测电力线的电压水平的下降以及开关控制电路，用于响应于电压检测器电路，关闭当前选择的块中除了升压功率开关之外的存储单元阵列的块中的升压功率开关。

23. 发明授权

US06611450B2 Ferroelectric random access memory 有权
公开(公告)号：US06611450B2
公开(公告)日：2003-08-26
申请号：US10087837
申请日：2002-03-05
申请人： Yukihito Oowaki , Sumiko Doumae
发明人： Yukihito Oowaki , Sumiko Doumae
IPC分类号： G11C700
CPC分类号： G11C11/22
摘要： A ferroelectric random access memory is disclosed, which comprises a cell array including a plurality of memory cells each having a ferroelectric memory device and a cell selecting transistor connected in series to the ferroelectric storage device, and imprint restricting circuit configured to restrict generation of an imprint by setting a polarization amount of a ferroelectric film of the ferroelectric memory device in the memory cell to an amount smaller than a polarization amount generated at a normal write time.

24. 发明授权

US06366490B1 Semiconductor memory device using ferroelectric film 有权
标题翻译：使用铁电薄膜的半导体存储器件
公开(公告)号：US06366490B1
公开(公告)日：2002-04-02
申请号：US09879054
申请日：2001-06-13
申请人： Yoshiaki Takeuchi , Yukihito Oowaki
发明人： Yoshiaki Takeuchi , Yukihito Oowaki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： This invention is such that, in a series-connected TC parallel-unit type ferroelectric RAM composed of a series connection of a plurality of unit cells, each unit cell being such that a ferroelectric capacitor is connected between the source and drain of a cell transistor, for instance, plate electrode wires are provided in the longitudinal direction of bit line pairs. The plate electrode wires are shared in memory block groups, each group being a set of a plurality of memory cell blocks connected to the same bit line pair. This causes only the memory cells read from or written into to be accessed by the selected word line and selected plate electrode wire in one select operation.
摘要翻译：本发明使得在由多个单元电池的串联连接构成的串联连接的TC并联单元型铁电RAM中，每个单电池使得在单电池晶体管的源极和漏极之间连接有铁电电容器例如，在位线对的长度方向上设置平板电极线。板电极线在存储块组中共享，每组是连接到同一位线对的多个存储单元块的集合。这将导致在一个选择操作中，所选择的字线和选定的板电极线只能读取或写入存储单元。

25. 发明授权

US6124744A Electronic circuit apparatus having circuits for effectively compensating for clock skew 失效
标题翻译：具有用于有效补偿时钟偏差的电路的电子电路装置
公开(公告)号：US6124744A
公开(公告)日：2000-09-26
申请号：US824743
申请日：1997-03-26
申请人： Yukihito Oowaki
发明人： Yukihito Oowaki
IPC分类号： G06F1/10 , H03K5/13 , H03K5/14
CPC分类号： G06F1/10 , H03K5/133 , H03K5/14
摘要： The present invention relates to, more specifically, an electronic circuit apparatus having a main system portion and a subsystem portion connected to the main system portion. In the electronic circuit apparatus, at least either the main system or the subsystem comprises a clock source, a clock wire having an outgoing path and an incoming path, wherein a clock signal from the clock source is inputted from one end of the outgoing path, and at least one receiver connected to an optional position of the outgoing path, further connected to a position of the outgoing path adjacent to the optional position, for supplying a clock signal having an optional delay level relative to the clock signal from the clock source according to a delay level between each clock signal at the positions.
摘要翻译：本发明更具体地涉及具有连接到主系统部分的主系统部分和子系统部分的电子电路装置。在电子电路装置中，主系统或子系统中的至少一个包括时钟源，具有输出路径的时钟线和输入路径，其中来自时钟源的时钟信号从输出路径的一端输入，以及连接到输出路径的可选位置的至少一个接收器，进一步连接到与可选位置相邻的输出路径的位置，以提供相对于来自时钟源的时钟信号具有可选延迟电平的时钟信号，根据到位置处的每个时钟信号之间的延迟水平。

26. 发明授权

US6087893A Semiconductor integrated circuit having suppressed leakage currents 失效
标题翻译：具有抑制泄漏电流的半导体集成电路
公开(公告)号：US6087893A
公开(公告)日：2000-07-11
申请号：US956956
申请日：1997-10-23
申请人： Yukihito Oowaki , Tsuneaki Fuse
发明人： Yukihito Oowaki , Tsuneaki Fuse
IPC分类号： H01L27/092 , G05F1/46 , G05F3/02 , H01L21/8238 , H01L29/786 , H03K17/687 , H03K19/0175 , H03K19/0948
CPC分类号： G05F1/46
摘要： A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.
摘要翻译：稳定的高速集成电路，由各种低电压驱动并消耗低功耗。使用MOSFET，其中向其栅极和主体施加信号以形成包括晶体管网络和至少一个缓冲电路的电路块。每个缓冲电路具有至少两种配置。在同一IC芯片上形成多个电路块。可以根据由电路块驱动的负载的电容的大小来选择缓冲电路的任何配置。

27. 发明授权

US5969998A MOS semiconductor device with memory cells each having storage capacitor and transfer transistor 有权
公开(公告)号：US5969998A
公开(公告)日：1999-10-19
申请号：US213773
申请日：1998-12-17
申请人： Yukihito Oowaki , Daisuke Kato , Daisaburo Takashima
发明人： Yukihito Oowaki , Daisuke Kato , Daisaburo Takashima
IPC分类号： G11C11/407 , G11C7/06 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4096 , G11C11/4091 , G11C7/065
摘要： A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode coupled to a word line and being connected between the capacitor and a bit line. Sense amplifier circuits are connected to the bit line pairs, and have a first and a second common source line. A decoder and a word line driver are connected to the word lines. A MOS transistor is connected between the power supply voltage and the first common source line, for selectively supplying it with a first voltage which potentially defines a high-level voltage for the bit line pairs. A voltage generator is connected through a MOS transistor to the second common source line, for generating a second voltage which potentially defines a low-level voltage for the bit line pairs, and which is selectively supplied to the second common source line. The second voltage is greater in potential than the ground potential, which is employed as a source voltage.

28. 发明授权

US5895956A Semiconductor memory device 失效
公开(公告)号：US5895956A
公开(公告)日：1999-04-20
申请号：US569844
申请日：1995-12-08
申请人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
发明人： Yukihito Oowaki , Masako Yoshida , Makoto Yoshimi
IPC分类号： H01L21/8242 , G11C11/4091 , H01L27/108 , H01L27/12 , H01L29/76 , H01L29/786 , H01L27/01
CPC分类号： G11C11/4091 , H01L27/10897 , H01L27/12
摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

29. 发明授权

US5867040A Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and reduce the voltage across any one transistor 失效
标题翻译：集成电路，具有Vcc和地之间的堆叠子电路，以节省功率并降低任何一个晶体管的电压
公开(公告)号：US5867040A
公开(公告)日：1999-02-02
申请号：US593275
申请日：1996-01-29
申请人： Tsuneaki Fuse , Yukihito Oowaki
发明人： Tsuneaki Fuse , Yukihito Oowaki
IPC分类号： G11C11/407 , G11C5/14 , H01L21/822 , H01L27/04 , H03K19/00 , H01L25/00
CPC分类号： G11C5/147 , H03K19/0016 , Y10T307/352
摘要： The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.
摘要翻译：本发明的半导体集成电路器件包括多个集成电路。调度电路从多个集成电路中选择任意数量的集成电路，并且将所选择的集成电路在电力线和接地线之间连接，使得所选择的集成电路串联或并联布置。调度电路设置所选择的集成电路的连接的组合，使得所选择的集成电路的总体的消耗功率变得最小。电压控制电路设定所选择的集成电路的串联连接部分的电位。数据控制电路具有用于在所选择的集成电路之间输入和输出数据的输入输出电路和外部，以及用于转换某些集成电路之间的数据电平的电平转换电路。

30. 发明授权

US5463577A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5463577A
公开(公告)日：1995-10-31
申请号：US365104
申请日：1994-12-28
申请人： Yukihito Oowaki , Takehiro Hasegawa
发明人： Yukihito Oowaki , Takehiro Hasegawa
IPC分类号： G11C11/41 , G11C8/12 , G11C8/14 , G11C11/22 , G11C11/401 , G11C11/404 , G11C11/407 , G11C11/24
CPC分类号： G11C8/12 , G11C8/14
摘要： There is provided a semiconductor memory having a reduced power consumption in data access and a high access speed in a NAND cell array scheme in which a memory cell unit is constituted by cascade-connecting a plurality of memory cells with each other. A memory cell array is divided into a plurality of sub-arrays, and the divided sub-arrays are selectively activated, thereby decreasing the capacitances of the word lines, register word lines, bit lines, and the like which are charged/discharged in data access.
摘要翻译：提供了一种在NAND单元阵列方案中数据访问中具有降低的功耗以及高存取速度的半导体存储器，其中通过将多个存储单元彼此级联连接而构成存储单元单元。存储单元阵列被分成多个子阵列，并且分割的子阵列被选择性地激活，从而减少在数据中被充电/放电的字线，寄存器字线，位线等的电容访问。

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