专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06617635B2 Integrated circuit devices having contact and container structures 有权
标题翻译：具有接触和容器结构的集成电路器件
公开(公告)号：US06617635B2
公开(公告)日：2003-09-09
申请号：US10039950
申请日：2001-12-31
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L27/10811 , H01L27/10852 , H01L28/84 , H01L28/90
摘要： Integrated circuitry fabricated using methods for forming contact structures and container structures, as described herein, are provided. The integrated circuitry formed by the methods of the present invention, for example DRAM structures, provide capacitors in containers having sufficiently high storage capacitance for advanced integrated circuit devices. In addition the methods for forming such container capacitors facilitate the formation of contacts structures and provided for the formation of local interconnect structures and electrical contact to each of the structures formed.
摘要翻译：提供了使用如本文所述形成接触结构和容器结构的方法制造的集成电路。通过本发明的方法（例如DRAM结构）形成的集成电路在具有足够高的存储电容的容器中提供用于高级集成电路器件的电容器。此外，用于形成这种容器电容器的方法有助于形成接触结构并且提供用于形成局部互连结构和与形成的每个结构的电接触。

22. 发明授权

US06605532B1 Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same 有权
公开(公告)号：US06605532B1
公开(公告)日：2003-08-12
申请号：US09858121
申请日：2001-05-15
申请人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
发明人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
IPC分类号： H01L214763
CPC分类号： H01L23/485 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.

23. 发明授权

US06383887B1 Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits 有权
标题翻译：形成电容器，DRAM阵列和单片集成电路的方法
公开(公告)号：US06383887B1
公开(公告)日：2002-05-07
申请号：US09724752
申请日：2000-11-28
申请人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
发明人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
IPC分类号： H01L2120
CPC分类号： H01L27/10888 , H01L27/10852 , H01L27/10855 , H01L28/82 , H01L28/84 , H01L28/90 , H01L29/94 , Y10S438/964
摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively lo forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.
摘要翻译：本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）基本上选择性地从暴露的未掺杂硅而不是暴露的掺杂硅形成凹凸多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

24. 发明授权

US06372601B1 Isolation region forming methods 失效
公开(公告)号：US06372601B1
公开(公告)日：2002-04-16
申请号：US09146838
申请日：1998-09-03
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L21762
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

25. 发明授权

US06331720B1 Electrically conductive structure 失效
标题翻译：导电结构
公开(公告)号：US06331720B1
公开(公告)日：2001-12-18
申请号：US09511514
申请日：2000-02-22
申请人： Kunal R. Parekh , Zhiqiang Wu , Li Li
发明人： Kunal R. Parekh , Zhiqiang Wu , Li Li
IPC分类号： H01L2708
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82
摘要： An electrically conductive structure, such as a capacitor is disclosed. A capacitor can be made by providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical strictures and within the trenches. Portions of the hard mask layer and the second group of the alternating layers of doped polysilicon and undoped polysilicon are selectively removed. An etch selective to the doped polysilicon is performed to selectively remove the undoped polysilicon to create an electrically conductive structure with spaced apart doped polysilicon layers. A dielectric layer and an electrically conductive cell plate are formed over the alternating layers of the doped polysilicon and the undoped polysilicon. The semiconductor substrate is heated to diffuse dopant in the doped polysilicon into the undoped polysilicon. The resultant novel capacitor has fin-like structure extending therefrom which increase the surface area thereof.
摘要翻译：公开了诸如电容器的导电结构。可以通过在半导体衬底上的一对栅极堆叠之间提供延伸的空间来形成电容器，该空间暴露半导体衬底上的电荷导电区域。在一对栅极叠层上形成BPSG层。在沉积多晶硅的单个沉积循环期间，在BPSG层上形成包括掺杂多晶硅和未掺杂多晶硅交替层的硬掩模层。选择性地去除硬掩模层和BPSG层的部分以形成在栅叠层之上延伸并且在它们之间具有沟槽的拓扑结构。执行间隔物蚀刻和接触蚀刻以暴露电荷导电区域。在每个形貌结构的侧面上形成掺杂的多晶硅间隔物。掺杂多晶硅和未掺杂多晶硅的第二组交替层形成在形貌上的狭缝和沟槽内。选择性地去除了硬掩模层和掺杂多晶硅和未掺杂多晶硅的交替层的第二组的部分。执行对掺杂多晶硅的选择性蚀刻以选择性地去除未掺杂的多晶硅以产生具有间隔开的掺杂多晶硅层的导电结构。在掺杂多晶硅和未掺杂多晶硅的交替层上形成介电层和导电单元板。加热半导体衬底以将掺杂多晶硅中的掺杂剂扩散到未掺杂的多晶硅中。所得到的新型电容器具有从其延伸的鳍状结构，其增加其表面积。

26. 发明授权

US06242816B1 Method for improving a stepper signal in a planarized surface over alignment topography 失效
标题翻译：一种用于在对准地形图上改善平坦化表面中的步进信号的方法
公开(公告)号：US06242816B1
公开(公告)日：2001-06-05
申请号：US09088322
申请日：1998-06-01
申请人： William A. Stanton , Phillip G. Wald , Kunal R. Parekh
发明人： William A. Stanton , Phillip G. Wald , Kunal R. Parekh
IPC分类号： H01L23544
CPC分类号： G03F9/7065 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.
摘要翻译：一种用于在半导体器件制造工艺中的对准步骤期间在半导体器件，组件或层压体中的不同材料的相邻层之间的界面处发生折射和反射的方法和结果。该方法包括在半导体器件，组件或层压体的衬底上形成具有第一折射率的材料的平面表面层。在平坦表面层上形成校正层，然后在校正层上形成具有第二折射率的第二层。校正层由在第一折射率和第二折射率之间具有中间折射率的材料组成。该方法还可以被修改为包括插入在任何上述相邻层之间或之上的一层或多层材料和/或中间折射层。可以通过在最上层上形成具有必要的中间折射率的附加材料层来进一步改进上述方法和所得结构，以进一步减少在最上层与空气之间的界面处发生的反射。本发明还涉及通过上述方法形成并结合上述结构的半导体器件，组件或层压体。

27. 发明授权

US06221711B1 Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry 失效
标题翻译：电接触导电插塞的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法
公开(公告)号：US06221711B1
公开(公告)日：2001-04-24
申请号：US09076324
申请日：1998-05-11
申请人： Martin Ceredig Roberts , Kunal R. Parekh
发明人： Martin Ceredig Roberts , Kunal R. Parekh
IPC分类号： H01L218242
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76802 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.
摘要翻译：描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。导电材料形成在开口内并与一个插头电连接。在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。暴露的顶部用第一绝缘材料封装。在衬底上形成第二不同绝缘材料层。通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。随后在容器中形成电容器。

28. 发明授权

US06214727B1 Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry 失效
公开(公告)号：US06214727B1
公开(公告)日：2001-04-10
申请号：US08798251
申请日：1997-02-11
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： H01L2144
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10817 , H01L27/10888 , H01L28/84 , H01L28/91
摘要： The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions. The invention includes a method of forming a contact to a node location comprising: a) forming an electrically insulative layer over a node location; b) patterning a masking layer over a portion of the insulative layer to form an unmasked portion and a masked portion of the insulative layer; c) removing parts of the masked and unmasked portions of the insulative layer to form a first opening over the node location which underlies a portion of the masking layer; d) forming an etch restriction layer within the first opening and over the masking layer; e) forming a sacrificial spacer layer within the first opening and over the etch restriction layer; f) forming a second opening extending from the first opening to the node location; and g) forming an electrically conductive pedestal within the first and second openings and in electrical connection with the node location. The invention also includes a capacitor comprising: a) an electrically conductive pedestal in electrical contact with a node location, the pedestal, viewed laterally in cross-section, comprising a pair of opposing lateral surfaces; b) an inner electrically conductive layer laterally against both lateral surfaces; c) a capacitor dielectric layer laterally against the inner conductive layer; and d) an outer electrically conductive layer laterally against the capacitor dielectric layer.

29. 发明授权

US06180485B2 Methods of forming capacitors, DRAM arrays, and monolithic integrated circuits 有权
标题翻译：形成电容器，DRAM阵列和单片集成电路的方法
公开(公告)号：US06180485B2
公开(公告)日：2001-01-30
申请号：US09323596
申请日：1999-06-01
申请人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
发明人： Kunal R. Parekh , John K. Zahurak , Phillip G. Wald
IPC分类号： H01L2120
CPC分类号： H01L27/10888 , H01L27/10852 , H01L27/10855 , H01L28/82 , H01L28/84 , H01L28/90 , H01L29/94 , Y10S438/964
摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.
摘要翻译：本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

30. 发明授权

US6015983A Bitline contact structures and DRAM array structures 失效
标题翻译：位线接触结构和DRAM阵列结构
公开(公告)号：US6015983A
公开(公告)日：2000-01-18
申请号：US93956
申请日：1998-06-08
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/10817 , H01L27/10888 , H01L27/10811 , H01L28/84 , H01L28/91
摘要： The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions. The invention includes a method of forming a contact to a node location comprising: a) forming an electrically insulative layer over a node location; b) patterning a masking layer over a portion of the insulative layer to form an unmasked portion and a masked portion of the insulative layer; c) removing parts of the masked and unmasked portions of the insulative layer to form a first opening over the node location which underlies a portion of the masking layer; d) forming an etch restriction layer within the first opening and over the masking layer; e) forming a sacrificial spacer layer within the first opening and over the etch restriction layer; f) forming a second opening extending from the first opening to the node location; and g) forming an electrically conductive pedestal within the first and second openings and in electrical connection with the node location. The invention also includes a capacitor comprising: a) an electrically conductive pedestal in electrical contact with a node location, the pedestal, viewed laterally in cross-section, comprising a pair of opposing lateral surfaces; b) an inner electrically conductive layer laterally against both lateral surfaces; c) a capacitor dielectric layer laterally against the inner conductive layer; and d) an outer electrically conductive layer laterally against the capacitor dielectric layer.
摘要翻译：本发明包括DRAM结构，电容器结构，导电触点，集成电路，形成DRAM结构的方法以及形成电容器结构的方法。本发明包括形成与节点位置的接触的方法，包括：a）在节点位置上形成电绝缘层; b）在绝缘层的一部分上图案化掩模层以形成绝缘层的未屏蔽部分和掩模部分; c）去除所述绝缘层的所述掩蔽和未掩模部分的部分，以在所述掩模层的一部分下方的所述节点位置上形成第一开口; d）在所述第一开口内和掩蔽层上形成蚀刻限制层; e）在所述第一开口内和所述蚀刻限制层上方形成牺牲间隔层; f）形成从所述第一开口延伸到所述节点位置的第二开口; 以及g）在所述第一和第二开口内形成导电基座并且与所述节点位置电连接。本发明还包括一种电容器，其包括：a）与节点位置电接触的导电基座，所述基座横截面横向看，包括一对相对的侧面; b）横向抵靠两个侧表面的内导电层; c）横向抵靠所述内导电层的电容器电介质层; 以及d）横向抵靠电容器介电层的外部导电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式