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1. 发明授权

US07071058B2 Methods of forming capacitors, and methods of forming DRAM circuitry 失效
标题翻译：形成电容器的方法以及形成DRAM电路的方法
公开(公告)号：US07071058B2
公开(公告)日：2006-07-04
申请号：US10817548
申请日：2004-04-02
申请人： Martin Ceredig Roberts , Christophe Pierrat
发明人： Martin Ceredig Roberts , Christophe Pierrat
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10855 , H01L28/91
摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.
摘要翻译：描述了电容器，DRAM电路及其形成方法。在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。第二容器与节点位置连接并且具有限定第二内部区域的开口。这些区域以不重叠的关系彼此间隔开。电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。轴是不同的并且彼此间隔开。在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。

2. 发明授权

US06727139B2 Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry 有权
标题翻译：电接触导电插塞的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法
公开(公告)号：US06727139B2
公开(公告)日：2004-04-27
申请号：US10273881
申请日：2002-10-17
申请人： Martin Ceredig Roberts , Kunal R. Parekh
发明人： Martin Ceredig Roberts , Kunal R. Parekh
IPC分类号： H01L218242
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76802 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.
摘要翻译：描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。导电材料形成在开口内并与一个插头电连接。在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。暴露的顶部用第一绝缘材料封装。在衬底上形成第二不同绝缘材料层。通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。随后在容器中形成电容器。

3. 发明授权

US06531352B1 Methods of forming conductive interconnects 有权
公开(公告)号：US06531352B1
公开(公告)日：2003-03-11
申请号：US09653151
申请日：2000-08-31
申请人： Gurtej S. Sandhu , Trung Tri Doan , Howard E. Rhodes , Sujit Sharan , Philip J. Ireland , Martin Ceredig Roberts
发明人： Gurtej S. Sandhu , Trung Tri Doan , Howard E. Rhodes , Sujit Sharan , Philip J. Ireland , Martin Ceredig Roberts
IPC分类号： H01L218238
CPC分类号： H01L21/76877 , H01L21/28518
摘要： The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.

4. 发明授权

US5907176A Integrated circuits and SRAM memory cells 失效
标题翻译：集成电路和SRAM存储单元
公开(公告)号：US5907176A
公开(公告)日：1999-05-25
申请号：US960874
申请日：1997-10-30
申请人： Martin Ceredig Roberts
发明人： Martin Ceredig Roberts
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/08 , H01L27/11
CPC分类号： H01L28/20 , H01L27/0802 , H01L27/11 , H01L27/1112 , Y10S257/904 , Y10S438/979
摘要： The invention encompasses integrated circuits and SRAM cells. In one aspect, the invention includes an integrated circuit comprising: a) an electrically insulative pillar extending substantially vertically outward of an underlying layer, the pillar having opposing substantially vertical side surfaces and a top, the pillar being taller than it is wide; b) a resistor comprising a layer of material which extends along both pillar vertical surfaces and over the top of the pillar; c) a first node in electrical connection with the resistor on one side of the insulative pillar; and d) a second node in electrical connection with the resistor on the other side of the insulative pillar.
摘要翻译：本发明包括集成电路和SRAM单元。一方面，本发明包括一种集成电路，包括：a）电绝缘柱，其基本上垂直向下延伸到底层的外侧，所述柱具有相对的基本上垂直的侧表面和顶部，所述柱比其宽; b）电阻器，其包括沿着所述支柱垂直表面延伸并且在所述柱的顶部上方延伸的材料层; c）与绝缘柱的一侧上的电阻器电连接的第一节点; 以及d）与绝缘柱的另一侧上的电阻器电连接的第二节点。

5. 发明授权

US5770496A Method of making a resistor 失效
标题翻译：制作电阻的方法
公开(公告)号：US5770496A
公开(公告)日：1998-06-23
申请号：US788617
申请日：1997-01-24
申请人： Martin Ceredig Roberts
发明人： Martin Ceredig Roberts
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/08 , H01L27/11 , H01L27/02
CPC分类号： H01L28/20 , H01L27/0802 , H01L27/11 , H01L27/1112 , Y10S257/904 , Y10S438/979
摘要： A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.
摘要翻译：从半导体材料形成电阻器的半导体处理方法包括：a）提供与电阻器进行电连接的节点; b）在节点外部提供第一电绝缘材料; c）在所述节点外部的所述第一电绝缘材料中提供暴露的垂直侧壁; d）在所述第一材料的外部和所述第一材料垂直侧壁上方提供第二电绝缘材料，所述第一和第二材料可相对于彼此选择性地蚀刻; e）相对于所述第一材料选择性地各向异性地蚀刻所述第二材料，以在所述第一材料垂直侧壁上方形成基本上垂直延伸的侧壁隔离物，并且向外暴露所述邻近所述侧壁间隔物的所述第一材料，所述间隔件具有内表面和外表面; f）相对于第二材料选择性地蚀刻第一材料以向外暴露间隔件外表面的至少一部分; g）在所述暴露的外隔离物表面上并在所述内间隔件表面上提供半导体材料的保形层，所述共形层与所述节点形成电连接; 以及h）将所述保形层图案化成所需的电阻器形状。公开了SRAM和其它集成电路的集成电路。

6. 发明授权

US5705843A Integrated circuits and SRAM memory cells 失效
标题翻译：集成电路和SRAM存储单元
公开(公告)号：US5705843A
公开(公告)日：1998-01-06
申请号：US679655
申请日：1996-07-12
申请人： Martin Ceredig Roberts
发明人： Martin Ceredig Roberts
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/08 , H01L27/11 , H01L21/70
CPC分类号： H01L28/20 , H01L27/0802 , H01L27/11 , H01L27/1112 , Y10S257/904 , Y10S438/979
摘要： SRAM and other integrated circuitry. In one aspect the invention includes an integrated circuit comprising: a) a first electrically insulating material layer having an outer surface; b) an electrically insulative pillar ring extending substantially vertically outward of the first layer, the pillar ring having opposing inner and outer substantially vertical side surfaces; c) an elongated resistor, the resistor comprising a layer of semiconductive material which serpentines over the first layer outer surface and the pillar ring vertical surfaces to form a container shape resistor within the pillar ring; d) an electrically conductive first node in electrical connection with the resistor on the inside of the insulative pillar ring; and e) an electrically conductive second node in electrical connection with the resistor on the outside of the insulative pillar ring.
摘要翻译： SRAM等集成电路。一方面，本发明包括一种集成电路，包括：a）具有外表面的第一电绝缘材料层; b）基本上垂直向外延伸的第一层的电绝缘柱环，所述柱环具有相对的内和外基本上垂直的侧表面; c）细长电阻器，所述电阻器包括在所述第一层外表面和所述柱环垂直表面上蛇形的半导体材料层，以在所述柱环内形成容器形电阻器; d）与绝缘柱环内侧的电阻器电连接的导电第一节点; 以及e）与所述绝缘柱环的外侧上的所述电阻器电连接的导电的第二节点。

7. 发明授权

US07060570B2 Methods of fabricating multiple sets of field effect transistors 失效
公开(公告)号：US07060570B2
公开(公告)日：2006-06-13
申请号：US10914825
申请日：2004-08-09
申请人： Fred D. Fishburn , Martin Ceredig Roberts
发明人： Fred D. Fishburn , Martin Ceredig Roberts
IPC分类号： H01L21/8232
CPC分类号： H01L21/31053 , H01L21/32139 , H01L21/82345 , H01L21/823828 , H01L21/823842 , Y10S438/941
摘要： The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

8. 发明授权

US06717201B2 Capacitor structure 失效
标题翻译：电容结构
公开(公告)号：US06717201B2
公开(公告)日：2004-04-06
申请号：US09198034
申请日：1998-11-23
申请人： Martin Ceredig Roberts , Christophe Pierrat
发明人： Martin Ceredig Roberts , Christophe Pierrat
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L28/91
摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.
摘要翻译：描述了电容器，DRAM电路及其形成方法。在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。第二容器与节点位置连接并且具有限定第二内部区域的开口。这些区域以不重叠的关系彼此间隔开。电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。轴是不同的并且彼此间隔开。在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。

9. 发明授权

US06475850B2 Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits 失效
标题翻译：用于制造集成电路的双极CMOS（BiCMOS）工艺
公开(公告)号：US06475850B2
公开(公告)日：2002-11-05
申请号：US09873808
申请日：2001-06-04
申请人： Michael Violette , Martin Ceredig Roberts
发明人： Michael Violette , Martin Ceredig Roberts
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO2/Si3N4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.
摘要翻译：使用最少数量的晶圆处理步骤制造BiCMOS集成电路，并提供IC电路设计器五（5）种不同的晶体管类型。这些类型包括P沟道和N沟道MOS晶体管以及三个不同的双极晶体管，其发射极都由不同的工艺形成，并且都以不同的电流增益和不同的击穿电压为特征。在IC制造工艺中使用差示二氧化硅/氮化硅掩蔽技术，其中使用单个掩模组在硅衬底中形成P型掩埋层（PBL）和N型掩埋层（NBL），并且其中P 类型的阱和N型阱在外延层上形成在这些掩埋层上方，也使用单个SiO 2 / Si 3 N 4差分掩模集合。两个双极晶体管发射极通过从第一和第二层多晶硅的扩散形成，而第三双极晶体管的发射极通过离子注入掺杂形成。

10. 发明授权

US06221711B1 Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry 失效
标题翻译：电接触导电插塞的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法
公开(公告)号：US06221711B1
公开(公告)日：2001-04-24
申请号：US09076324
申请日：1998-05-11
申请人： Martin Ceredig Roberts , Kunal R. Parekh
发明人： Martin Ceredig Roberts , Kunal R. Parekh
IPC分类号： H01L218242
CPC分类号： H01L21/76838 , H01L21/768 , H01L21/76802 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion. The exposed top portion is encapsulated with a first insulating material. A layer of second different insulating material is formed over the substrate. Portions of the second insulating material are removed selectively relative to the first insulating material over the conductive plugs on each side of the conductive lines to provide a pair of capacitor containers. Capacitors are subsequently formed in the containers.
摘要翻译：描述了与导电插塞电接触的方法，形成接触开口的方法以及形成动态随机存取存储器电路的方法。在一个实施例中，形成一对导电接触插塞相对于半导体晶片向外突出。插头具有相应的顶部，其中一个顶部覆盖有不同的第一和第二绝缘材料。通过第一绝缘材料和第二绝缘材料之一蚀刻开口以露出该对插头的顶部中的一个。导电材料形成在开口内并与一个插头电连接。在优选实施例中，在衬底上形成两个间隔开的导电线，并且在导电线的每一侧之间和之间形成导电插塞。形成在导电线之间的导电插塞提供具有至少部分暴露的顶部的位线接触插头。暴露的顶部用第一绝缘材料封装。在衬底上形成第二不同绝缘材料层。通过在导电线的每一侧上的导电插塞上相对于第一绝缘材料选择性地去除第二绝缘材料的部分，以提供一对电容器容器。随后在容器中形成电容器。

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