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21. 发明授权

US07749845B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07749845B2
公开(公告)日：2010-07-06
申请号：US11988944
申请日：2006-06-26
申请人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
发明人： Shigeharu Yamagami , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Yoshio Shimoida
IPC分类号： H01L21/336
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
摘要翻译：一种制造具有多晶硅层（5）的半导体器件的方法包括：在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。

22. 发明申请

US20090200575A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090200575A1
公开(公告)日：2009-08-13
申请号：US12423207
申请日：2009-04-14
申请人： Yoshio SHIMOIDA , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio SHIMOIDA , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate.
摘要翻译：半导体器件设置有半导体区域，栅极电极，源极电极和漏极电极。半导体区域形成在半导体衬底表面上，并且包括第一导电类型的第一半导体部分，第二导电类型的第二半导体部分，与衬底带隙不同的带隙，多于两个的累积半导体层，以及层之间的交叉点。半导体层各自含有第一导电类型的杂质。栅极通过栅极绝缘膜与第二半导体部分和半导体衬底之间的异质结相邻。源电极耦合到半导体区域。漏电极耦合到半导体衬底。

23. 发明授权

US07436004B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07436004B2
公开(公告)日：2008-10-14
申请号：US11289460
申请日：2005-11-30
申请人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L31/111
CPC分类号： H01L29/7398 , H01L29/0834 , H01L29/1608 , H01L29/267 , H01L29/7391 , H01L29/7392 , H01L29/7395 , H01L29/7397
摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.
摘要翻译：本发明的一个方面提供一种半导体器件，其包括：第一导电类型的第一半导体本体，设置在第一半导体本体上的第一开关机构，被配置和布置成用于接通流过半导体器件的导通/截止电流;以及设置在所述半导体本体上的第一反向阻挡异质结二极管，被配置和布置成阻止与所述第一开关机构相反的电流接通/断开。

24. 发明申请

US20060223274A1 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US20060223274A1
公开(公告)日：2006-10-05
申请号：US11377909
申请日：2006-03-16
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P− type impurity in a polycrystalline silicon layer formed on an N− type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.

25. 发明授权

US07880199B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07880199B2
公开(公告)日：2011-02-01
申请号：US11790791
申请日：2007-04-27
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Yoshio Shimoida , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/66
CPC分类号： H01L29/0847 , H01L29/1033 , H01L29/1608 , H01L29/267 , H01L29/4916 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing portion in the hetero semiconductor region which is positioned to face toward the gate electrode through the gate insulator layer.
摘要翻译：半导体器件具有：预定的导电型的半导体衬底; 与所述半导体衬底的第一主表面接触并且包括具有与所述半导体衬底的带隙不同的带隙的半导体材料的异质半导体区域; 在与所述异质半导体区域和所述半导体基板之间的接合区域相邻的位置处形成的栅极电极，连接到所述异质半导体区的源电极; 和连接到半导体衬底的漏电极; 其中所述异质半导体区域包括与所述源电极接触的接触部分，所述接触部分的至少一部分区域具有与所述半导体衬底的导电型相同的导电类型，并且所述部分区域的杂质浓度高于至少通过栅极绝缘体层位于面向栅电极的异质半导体区域中的栅电极面对部分的部分区域的杂质浓度。

26. 发明授权

US07859015B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07859015B2
公开(公告)日：2010-12-28
申请号：US12423207
申请日：2009-04-14
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L31/072
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate.
摘要翻译：半导体器件设置有半导体区域，栅极电极，源极电极和漏极电极。半导体区域形成在半导体衬底表面上，并且包括第一导电类型的第一半导体部分，第二导电类型的第二半导体部分，与衬底带隙不同的带隙，多于两个的累积半导体层，以及层之间的交叉点。半导体层各自含有第一导电类型的杂质。栅极通过栅极绝缘膜与第二半导体部分和半导体衬底之间的异质结相邻。源电极耦合到半导体区域。漏电极耦合到半导体衬底。

27. 发明授权

US07781802B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07781802B2
公开(公告)日：2010-08-24
申请号：US11790679
申请日：2007-04-26
申请人： Shigeharu Yamagami , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka
发明人： Shigeharu Yamagami , Masakatsu Hoshi , Yoshio Shimoida , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L21/4763
CPC分类号： H01L29/8613 , H01L21/0465 , H01L21/0475 , H01L29/0615 , H01L29/1608 , H01L29/267 , H01L29/6606 , H01L29/66136
摘要： As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N− silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode. Moreover, the N+ polycrystalline silicon layer of the same conduction type as the conduction type of the semiconductor base is formed so as to contact the first main surface of the semiconductor base, and the P+ polycrystalline silicon layer of the conduction type different from the conduction type of the semiconductor base is formed in trenches dug on the first main surface of the semiconductor base.
摘要翻译：作为与通过在与阴极连接的N +碳化硅衬底上形成N-碳化硅外延层而构成的半导体衬底的第一主表面接触的半导体区域，提供了具有相同导电性的N +多晶硅层类型为半导体基底的导电类型和不同于半导体基底的导电类型的导电类型的P +多晶硅层。 N +多晶硅层和P +多晶硅层都与半导体基体异相接合，并与欧姆连接到阳极电极。此外，形成与半导体基底的导电类型相同的导电类型的N +多晶硅层，以便与半导体基底的第一主表面接触，并且与导电类型不同的导电类型的P +多晶硅层形成在半导体基底的第一主表面上的沟槽中。

28. 发明授权

US07714352B2 Hetero junction semiconductor device 有权
标题翻译：异质结半导体器件
公开(公告)号：US07714352B2
公开(公告)日：2010-05-11
申请号：US11701429
申请日：2007-02-02
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L31/0312 , H01L31/036 , H01L29/10 , H01L29/93
CPC分类号： H01L29/267 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.
摘要翻译：一种半导体器件，包括：第一导电半导体衬底; 用于与第一导电半导体衬底形成异质结的异质半导体区域; 通过栅绝缘膜与所述异质结的一部分相邻的栅电极; 连接到所述第一导电半导体衬底的漏电极; 连接到所述异质半导体区域的源电极; 以及第二导电半导体区域，形成在第一导电半导体基板的第一面的一部分上，以与栅电极相对的方式经由栅极绝缘膜，栅极绝缘膜，异质半导体区域和第一导电半导体区域导电性半导体基板彼此接触，从而形成三重接触点。第二导电率半导体区域的第一面具有允许来自栅电极的场在第二导电半导体区域的第一面上形成反型层的杂质浓度。

29. 发明授权

US07695997B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07695997B2
公开(公告)日：2010-04-13
申请号：US11790792
申请日：2007-04-27
申请人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Tetsuya Hayashi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L21/00 , H01L31/072
CPC分类号： H01L27/0255 , H01L28/20 , H01L29/1608 , H01L29/161 , H01L29/267 , H01L29/66068 , H01L29/7828 , H01L29/866
摘要： An electrostatic discharge protection element and a protection resistor, which are formed on an N− drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal. Semiconductor regions of the first layer and the second layer are formed by using semiconductor films, which form a hetero semiconductor region and the gate electrode, respectively.
摘要翻译：为了防止场效应晶体管的电击穿而形成在其上具有场氧化物膜的N-漏极区域上的静电放电保护元件和保护电阻器被构成为一个或多个二极管的叠层双向齐纳二极管，第一层的多个N +多晶硅区域和第二层的P +多晶硅区域，以及第一层的一个或多个N +电阻层和第二层的N +电阻层的层叠电阻器。第一层的多个N +多晶硅区域的一端连接到外部栅电极端子，另一端与源电极连接。第一层的多个N +电阻层的一端连接到栅电极，另一端连接到外部栅电极端子。通过使用分别形成杂半导体区域和栅电极的半导体膜来形成第一层和第二层的半导体区域。

30. 发明申请

US20090267113A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090267113A1
公开(公告)日：2009-10-29
申请号：US12066145
申请日：2006-08-02
申请人： Yoshio Shimoida , Tetsuya Hayashi , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
发明人： Yoshio Shimoida , Tetsuya Hayashi , Masakatsu Hoshi , Hideaki Tanaka , Shigeharu Yamagami
IPC分类号： H01L29/267 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/0445 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semi-conductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.
摘要翻译：半导体器件具有第一导电类型的半导体基底; 与半导体基底接触的异质半导体区域; 与栅极绝缘膜相邻的异质半导体区域和半导体基底之间的结的部分相邻的栅电极; 连接到所述异质半导体区的源电极; 以及连接到半导体基底的漏电极。异质半导体区域具有与半导体基底不同的带隙。异质半导体区域包括第一异质半导体区域和第二异质半导体区域。在形成栅极绝缘膜之前形成第一异质半导体区域。在形成栅极绝缘膜之后形成第二异质半导体区域。

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