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21. 发明申请

US20090075466A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090075466A1
公开(公告)日：2009-03-19
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

22. 发明授权

US07521321B2 Method of fabricating a non-volatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US07521321B2
公开(公告)日：2009-04-21
申请号：US11693716
申请日：2007-03-30
申请人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Ming-Hsiang Hsueh , Erh-Kun Lai , Chia-Wei Wu , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/28282 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.
摘要翻译：本发明涉及一种存储器件及其制造方法。存储器件包括衬底，衬底上的隧道电介质膜，形成在衬底中的源区和漏区对，以及在每对源区和漏区之间的多个分开的存储块。每个存储线块包括存储介质和二氧化硅层。两个存储块以至少100埃的间隔分开。

23. 发明授权

US07879706B2 Memory and manufacturing method thereof 有权
标题翻译：其记忆及其制造方法
公开(公告)号：US07879706B2
公开(公告)日：2011-02-01
申请号：US11979101
申请日：2007-10-31
申请人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
发明人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/66545 , H01L29/66583 , H01L29/7923
摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
摘要翻译：提供具有隔离双存储单元的存储器。第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。

24. 发明授权

US07785963B2 Method for fabricating inverted T-shaped floating gate memory 有权
标题翻译：倒T形浮栅存储器的制造方法
公开(公告)号：US07785963B2
公开(公告)日：2010-08-31
申请号：US12036196
申请日：2008-02-22
申请人： Ming-Hsiang Hsueh , Yen-Hao Shih , Erh-Kun Lai
发明人： Ming-Hsiang Hsueh , Yen-Hao Shih , Erh-Kun Lai
IPC分类号： H01L21/8239
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.
摘要翻译：公开了具有非矩形横截面的浮动栅极的存储器件。非矩形横截面可以是倒T形，梯形或双倒T形。公开了用于制造由于浮动栅极的增加的表面积而具有改进的耦合比的浮动栅极存储器件的方法。存储器件具有浮动栅极，其具有诸如倒T形的横截面形状，使得顶部轮廓不是平坦的线段。

25. 发明申请

US20100117049A1 MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS 有权
标题翻译：具有多晶硅管和单晶半导体区域的PN结的存储器单元访问器件
公开(公告)号：US20100117049A1
公开(公告)日：2010-05-13
申请号：US12267492
申请日：2008-11-07
申请人： HSIANG-LAN LUNG , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
发明人： HSIANG-LAN LUNG , Erh-Kun Lai , Yen-Hao Shih , Yi-Chou Chen , Shih-Hung Chen
IPC分类号： H01L47/00 , H01L21/36
CPC分类号： H01L45/1233 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L29/861 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683
摘要： A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.
摘要翻译：存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

26. 发明申请

US20060205157A1 Non-volatile memory and method for fabricating the same 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060205157A1
公开(公告)日：2006-09-14
申请号：US11429070
申请日：2006-05-05
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.
摘要翻译：提供非易失性存储器。存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。其中介电层设置在基板上。导电层设置在电介质层上。隔离层设置在基板上并且邻近电介质层和导电层。掩埋位线设置在衬底中并在隔离层下方。隧道电介质层设置在导电层和隔离层的基板和侧壁上。电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。字线设置在基板上，与埋入位线交叉。

27. 发明授权

US07067375B1 Non-volatile memory and method for fabricating the same 有权
公开(公告)号：US07067375B1
公开(公告)日：2006-06-27
申请号：US11018507
申请日：2004-12-20
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42348 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

28. 发明授权

US08816423B2 Semiconducting multi-layer structure and method for manufacturing the same 有权
标题翻译：半导体多层结构及其制造方法
公开(公告)号：US08816423B2
公开(公告)日：2014-08-26
申请号：US13584366
申请日：2012-08-13
申请人： Erh-Kun Lai , Yen-Hao Shih
发明人： Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A semiconducting multi-layer structure comprising a plurality of first conductive layers, a plurality of first insulating layers and a second conductive layer is disclosed. The first conductive layers are separately disposed. Each of the first conductive layers has an upper surface, a bottom surface opposite to the upper surface and a lateral surface. The first insulating layers surround the peripherals of the first conductive layers. Each of the first insulating layers covers at least a part of the upper surface of each of the first conductive layers, at least a part of the bottom surface of each of the first conductive layers and the two lateral surface of each of the first conductive layers. The second conductive layer covers the first conductive layers and the first insulating layers.
摘要翻译：公开了一种包括多个第一导电层，多个第一绝缘层和第二导电层的半导体多层结构。第一导电层分开设置。每个第一导电层具有上表面，与上表面相对的底表面和侧表面。第一绝缘层围绕第一导电层的外围设备。每个第一绝缘层覆盖每个第一导电层的上表面的至少一部分，每个第一导电层的底表面的至少一部分和每个第一导电层的两个侧表面。第二导电层覆盖第一导电层和第一绝缘层。

29. 发明授权

US08437192B2 3D two bit-per-cell NAND flash memory 有权
标题翻译： 3D双比特单元NAND闪存
公开(公告)号：US08437192B2
公开(公告)日：2013-05-07
申请号：US12785291
申请日：2010-05-21
申请人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
发明人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
IPC分类号： G11C16/00 , G11C16/02 , G11C16/04 , G11C5/02 , G11C5/06
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。包括导电材料层的共同源平面位于顶部和底部存储立方体之间。源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

30. 发明申请

US20050237815A1 Operation scheme with charge balancing erase for charge trapping non-volatile memory 有权
标题翻译：具有电荷平衡擦除的电荷捕获非易失性存储器的操作方案
公开(公告)号：US20050237815A1
公开(公告)日：2005-10-27
申请号：US10876377
申请日：2004-06-24
申请人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh
发明人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh
IPC分类号： G11C16/02 , G11C16/04 , G11C16/14 , G11C16/30 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/14 , G11C16/30
摘要： A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge in the charge trapping structure, and a second bias arrangement tending to the induce balanced charge tunneling between the gate and the charge trapping structure and between the charge trapping structure in the channel. A second procedure (typically program) is used to establish a high threshold state in the memory cell, including a third bias arrangement that causes an increase in negative charge in the charge trapping structure.
摘要翻译：一种操作存储器单元的方法包括施加第一过程（通常是擦除）以建立低阈值状态，包括引起电荷俘获结构中的负电荷减小的第一偏置装置，以及倾向于引起平衡电荷隧穿的第二偏置装置在栅极和电荷捕获结构之间以及沟道中的电荷捕获结构之间。第二程序（通常为程序）用于在存储器单元中建立高阈值状态，包括导致电荷俘获结构中的负电荷增加的第三偏置装置。

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