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21. 发明授权

US06198134B1 Semiconductor device having a common substrate bias 失效
标题翻译：具有公共衬底偏置的半导体器件
公开(公告)号：US06198134B1
公开(公告)日：2001-03-06
申请号：US09056616
申请日：1998-04-08
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L2701
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

22. 发明授权

US5937284A Method of making a semiconductor device having an SOI structure 失效
标题翻译：制造具有SOI结构的半导体器件的方法
公开(公告)号：US5937284A
公开(公告)日：1999-08-10
申请号：US979621
申请日：1997-11-28
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Tadashi Nishimura
IPC分类号： H01L27/12 , H01L21/00 , H01L21/425 , H01L21/76
CPC分类号： H01L27/1203
摘要： Generation of parasitic transistor in active layer edge is prevented. In an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.
摘要翻译：防止有源层边缘中的寄生晶体管的产生。在绝缘膜（20）上的半导体层（21）的NMOS区域中，使用氮化膜（23）和抗蚀剂（253a）作为掩模，通过旋转倾斜注入注入硼离子。在通过LOCOS方法分离元件的区域附近，即仅在作为NMOS晶体管的有源层的半导体层（21）的边缘区域中，硼离子注入约3×10 13 / cm 2。在LOCOS氧化之后，杂质浓度提高到这样的水平，因为硼离子可能不被吸入氧化膜中。

23. 发明授权

US5801080A Method of manufacturing semiconductor substrate having total and partial dielectric isolation 失效
标题翻译：制造具有全部和部分电介质隔离的半导体衬底的方法
公开(公告)号：US5801080A
公开(公告)日：1998-09-01
申请号：US837959
申请日：1997-04-14
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/84 , H01L23/482 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

24. 发明授权

US5652454A Semiconductor device on an SOI substrate 失效
标题翻译： SOI衬底上的半导体器件
公开(公告)号：US5652454A
公开(公告)日：1997-07-29
申请号：US675510
申请日：1996-07-03
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/84 , H01L23/482 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H01L27/01 , H01L23/58 , H01L29/00
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

25. 发明授权

US5381235A Three-dimensional shape measuring device and three-dimensional shape measuring sensor 失效
标题翻译：三维形状测量装置和三维形状测量传感器
公开(公告)号：US5381235A
公开(公告)日：1995-01-10
申请号：US990460
申请日：1992-12-15
申请人： Yasuo Inoue , Tadashi Nishimura , Takashi Ipposhi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Takashi Ipposhi , Toshiaki Iwamatsu
IPC分类号： G01B11/24 , G01B11/02 , G01B11/25 , G01C3/06 , H01L27/14
CPC分类号： G01B11/024 , G01B11/2518
摘要： The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device. The three-dimensional shape measuring device comprises a light source for scanning plane light over the surface of an object, an image sensor opposed to the object and provided with a plurality of pixels, an optical system for forming an image of a bright line appearing on the surface of the object due to plane light on the image sensor, a plurality of capacitors installed in association with pixels of the image sensor, a charger for storing given charges in a plurality of capacitors before plane light scanning starts, a plurality of dischargers lying in association with capacitors and gradually discharging the capacitors for pixels corresponding to a bright line image from when plane light scanning starts until the bright line image passes through the pixels, and an arithmetic logic means for computing charges remaining in the plurality of capacitors after plane light scanning is completed and thus providing a three-dimensional shape of an object. Thereby, a three-dimensional shape of an object can be measured at a high speed with high precision.
摘要翻译：本发明提供了三维形状测量装置和用于三维形状测量装置的传感器。三维形状测量装置包括：用于扫描物体表面上的平面光的光源，与该物体相对并设置有多个像素的图像传感器，用于形成亮线的图像的光学系统，由于图像传感器上的平面光，物体的表面，与图像传感器的像素相关联地安装的多个电容器，用于在平面光扫描开始之前在多个电容器中存储给定电荷的充电器，多个放电器位于与平面光扫描开始直到亮线图像通过像素的与亮线图像相对应的像素的电容器逐渐放电;以及算术逻辑装置，用于计算平面光后的多个电容器中剩余的电荷扫描完成，从而提供对象的三维形状。由此，可以高精度地测量物体的三维形状。

26. 发明授权

US5283455A Thin film field effect element having an LDD structure 失效
标题翻译：具有LDD结构的薄膜场效应元件
公开(公告)号：US5283455A
公开(公告)日：1994-02-01
申请号：US911582
申请日：1992-07-10
申请人： Yasuo Inoue , Tadashi Nishimura , Motoi Ashida
发明人： Yasuo Inoue , Tadashi Nishimura , Motoi Ashida
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L29/76 , H01L27/01 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6675 , H01L29/66765 , H01L29/78624 , H01L29/78642
摘要： An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.
摘要翻译：在绝缘基板上形成的栅电极的上表面上形成上绝缘层。栅极绝缘层形成在栅电极的侧壁和上绝缘层的表面上。在栅极绝缘层的表面上形成半导体层。在半导体层中形成三个源/漏区。沿着栅电极的两个侧表面在半导体层中形成两个独立的沟道区。源极/漏极区域布置在两个沟道区域的两端。每个源极/漏极区域具有通过倾斜离子注入方法以自对准方式形成的LDD结构和使用在沟道区上形成的侧壁绝缘层作为掩模的垂直离子注入方法。

27. 发明授权

US5001539A Multiple layer static random access memory device 失效
标题翻译：多层静态随机存取存储器件
公开(公告)号：US5001539A
公开(公告)日：1991-03-19
申请号：US337702
申请日：1989-04-13
申请人： Yasuo Inoue , Tadashi Nishimura
发明人： Yasuo Inoue , Tadashi Nishimura
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/1108 , Y10S257/903
摘要： A stacked static random access memory SRAM having a plurality of memory cells is disclosed. Individual memory cell has a portion formed in an upper active element layer in the device structure and a portion formed in a lower active element layer in the device structure separated from the upper layer by an intermediate insulating layer. A word line, a bit line and access transistors are formed in the same upper active element layer, eliminating the need for interconnecting them through the insulating layer. The elimination of the inter-layer connections helps to reduce the number of through-holes required to be made in the insulating layer. This in turn reduces the area to be occupied by the memory cell and leads to a simplified manufacturing process of the SRAM.
摘要翻译：公开了一种具有多个存储单元的堆叠静态随机存取存储器SRAM。单个存储单元具有形成在器件结构中的上有源元件层中的部分，以及通过中间绝缘层与器件结构中的下有源元件层中形成的部分形成在上层中的部分。在相同的上部有源元件层中形成字线，位线和存取晶体管，消除了通过绝缘层将它们互连的需要。层间连接的消除有助于减少在绝缘层中制造的通孔的数量。这又减少了由存储器单元占用的面积，并导致了SRAM的简化制造过程。

28. 发明授权

US4987092A Process for manufacturing stacked semiconductor devices 失效
标题翻译：叠层半导体器件的制造方法
公开(公告)号：US4987092A
公开(公告)日：1991-01-22
申请号：US204581
申请日：1988-06-09
申请人： Kiyoteru Kobayashi , Tadashi Nishimura , Hiroshi Morita , Shuji Nakao , Hidekazu Oda , Yasuo Inoue
发明人： Kiyoteru Kobayashi , Tadashi Nishimura , Hiroshi Morita , Shuji Nakao , Hidekazu Oda , Yasuo Inoue
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/822 , H01L21/8244 , H01L27/00 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L27/11 , H01L21/8221 , H01L27/1104 , H01L27/1108
摘要： An improved method of manufacturing semiconductor devices having a stacked structure is disclosed. A p-channel semiconductor substrate is prepared, and on the major surface of the substrate, n-channel source and drain regions and a gate electrode are formed to provide a n-channel transistor. Sidewalls are formed of P type single-crystal silicon on the opposite size of the gate electrode of n-channel transistor with an insulating layer interposed between the sidewalls and the gate electrode. A single-crystal layer covers the source, drain and gate electrode of the n-channel transistor and the sidewall structures. A P type impurity present in the sidewalls is diffused into the single-crystal layer.
摘要翻译：公开了一种制造具有堆叠结构的半导体器件的改进方法。制备p沟道半导体衬底，并且在衬底的主表面上形成n沟道源极和漏极区域以及栅极电极以提供n沟道晶体管。侧壁由位于n沟道晶体管的栅电极的相对尺寸上的P型单晶硅形成，其中介于侧壁和栅电极之间的绝缘层。单晶层覆盖了n沟道晶体管的源极，漏极和栅极以及侧壁结构。存在于侧壁中的P型杂质扩散到单晶层中。

29. 发明授权

US06727552B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06727552B2
公开(公告)日：2004-04-27
申请号：US10062462
申请日：2002-02-05
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L2701
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

30. 发明授权

US06649976B2 Semiconductor device having metal silicide film and manufacturing method thereof 失效
公开(公告)号：US06649976B2
公开(公告)日：2003-11-18
申请号：US09982777
申请日：2001-10-22
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L2976
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

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