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21. 发明授权

US08976597B2 Electrically rewriteable nonvolatile semiconductor memory device 有权
标题翻译：电可重写非易失性半导体存储器件
公开(公告)号：US08976597B2
公开(公告)日：2015-03-10
申请号：US13227050
申请日：2011-09-07
申请人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
IPC分类号： G11C11/34 , G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/16 , G11C16/3445 , G11C16/345
摘要： A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.
摘要翻译：控制电路执行包括擦除脉冲施加操作和擦除验证操作的擦除操作。擦除脉冲施加操作将擦除脉冲电压施加到存储单元，以将存储单元从写入状态改变为擦除状态。擦除验证操作将擦除验证电压施加到存储器单元以判断存储器单元是否处于擦除状态。当在一个擦除操作中执行擦除脉冲施加操作的次数达到第一数量时，控制电路改变擦除验证操作的执行条件。

22. 发明授权

US08605514B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08605514B2
公开(公告)日：2013-12-10
申请号：US12885066
申请日：2010-09-17
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C11/40
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory cell, a second memory cell, and a control circuit. The first memory cell is connected to a first word line. The second memory cell is connected to a second word line which is adjacent to the first word line and has a width different from a width of the first word line. The control circuit applies a first voltage to the first word line and a second voltage different from the first voltage to the second word line. At least one of the first voltage and the second voltage is corrected by the control circuit based on write loop counts of the first memory cell and the second memory cell when the first memory cell and the second memory cell are write target cells in a write operation.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一存储单元，第二存储单元和控制电路。第一存储单元连接到第一字线。第二存储单元连接到与第一字线相邻的第二字线，并且具有与第一字线的宽度不同的宽度。控制电路将第一电压施加到第一字线，并将第一电压与第一电压不同于第二字线。当第一存储单元和第二存储单元在写入操作中写入目标单元时，基于第一存储单元和第二存储器单元的写入循环计数，控制电路校正第一电压和第二电压中的至少一个电压。

23. 发明授权

US08599617B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08599617B2
公开(公告)日：2013-12-03
申请号：US13457560
申请日：2012-04-27
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

24. 发明授权

US08422301B2 Nonvolatile semiconductor memory device and operating method thereof 失效
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US08422301B2
公开(公告)日：2013-04-16
申请号：US13169414
申请日：2011-06-27
申请人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
摘要翻译：根据实施例的非易失性半导体存储器件包括存储单元阵列。控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作值小于第一升压值。

25. 发明申请

US20120206968A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120206968A1
公开(公告)日：2012-08-16
申请号：US13457560
申请日：2012-04-27
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
摘要翻译：非易失性半导体存储器件包括：控制电路，被配置为控制将非易失性存储器单元设置为非易失性存储单元的第一阈值电压分布状态的软编程操作。当非易失性存储单元的特性处于第一状态时，控制电路通过将用于将非易失性存储单元设置为第一阈值电压分布状态的第一电压施加到第一字线来执行软编程操作，并且施加第二电压高于第一个电压到第二个字线。当非易失性存储单元的特性处于第二状态时，控制电路通过向第一字线施加等于或低于第一电压的第三电压并施加低于第二电压的第四电压来执行软编程操作到第二个字线。

26. 发明申请

US20110063917A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110063917A1
公开(公告)日：2011-03-17
申请号：US12878624
申请日：2010-09-09
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
摘要翻译：非易失性半导体存储器件包括：控制电路，被配置为控制将非易失性存储器单元设置为非易失性存储单元的第一阈值电压分布状态的软编程操作。当非易失性存储单元的特性处于第一状态时，控制电路通过将用于将非易失性存储单元设置为第一阈值电压分布状态的第一电压施加到第一字线来执行软编程操作，并且施加第二电压高于第一个电压到第二个字线。当非易失性存储单元的特性处于第二状态时，控制电路通过向第一字线施加等于或低于第一电压的第三电压并施加低于第二电压的第四电压来执行软编程操作到第二个字线。

27. 发明授权

US06877910B2 Plastic ferrule 失效
标题翻译：塑料套圈
公开(公告)号：US06877910B2
公开(公告)日：2005-04-12
申请号：US10272002
申请日：2002-10-17
申请人： Eietsu Takahashi , Kazuo Nomura , Susumu Yamamoto , Hiroshi Matsumiya , Osamu Daikuhara , Shinichiro Kawaguchi , Noboru Shimizu , Hideo Miyazawa , Koji Watanabe , Hirohiko Tsugane , Naoki Ikemori
发明人： Eietsu Takahashi , Kazuo Nomura , Susumu Yamamoto , Hiroshi Matsumiya , Osamu Daikuhara , Shinichiro Kawaguchi , Noboru Shimizu , Hideo Miyazawa , Koji Watanabe , Hirohiko Tsugane , Naoki Ikemori
IPC分类号： G02B6/36 , B29C45/14 , B29C45/16 , B29C45/36 , B29K105/20 , B29L11/00 , B29L31/36 , G02B6/38
CPC分类号： G02B6/3835 , B29C45/16 , B29C45/1615 , B29C45/1676 , B29L2011/0075 , G02B6/3865 , Y10T16/39
摘要： A plastic ferrule including a centering section having a tubular body. The tubular body is provided with an outer-circumferential centering reference surface and a center axis of the centering reference surface. The centering section includes a resinous outer tube part having the outer-circumferential centering reference surface and provided, along the center axis, with a coated-fiber holding bore for securely accommodating a coated optical fiber and a fixing bore extending from the coated-fiber holding bore, the outer tube part forming a tubular wall with a generally uniform thickness as a whole. The centering section also includes an inner tube part fixed to the fixing bore of the outer tube part and provided along the center axis with an uncoated-fiber holding bore, communicating with the coated-fiber holding bore, for securely accommodating an uncoated optical fiber.
摘要翻译：一种塑料套管，包括具有管状体的定心部分。管体具有外圆周对中基准面和中心基准面的中心轴线。定心部包括具有外圆周对中面的树脂外管部，沿着中心轴线设置有用于牢固地容纳被覆光纤的涂布纤维保持孔和从涂覆光纤保持件延伸的固定孔孔，外管部分形成整体上具有大致均匀厚度的管状壁。中心部分还包括固定到外管部分的固定孔的内管部分，并且沿着中心轴线设置有与涂覆纤维保持孔连通的未涂覆纤维保持孔，用于牢固地容纳未涂覆的光纤。

28. 发明授权

US08867277B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08867277B2
公开(公告)日：2014-10-21
申请号：US13601233
申请日：2012-08-31
申请人： Tatsuo Izumi , Eietsu Takahashi
发明人： Tatsuo Izumi , Eietsu Takahashi
IPC分类号： G11C11/34 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/30
CPC分类号： G11C16/12 , G11C16/08 , G11C16/10 , G11C16/30
摘要： A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.
摘要翻译：包括与选定字线相邻的字线的第一非选择字线被施加第一写通电压。此外，作为除了第一未选择字线之外的未选择字线的第二非选择字线被施加小于编程电压的第二写入通过电压。在写入操作中，控制电路通过执行具有第一电压上升幅度X倍的升压动作将第一写入通过电压提高到第一目标值，并且通过执行第二写入通过电压向第二目标值升高第二写入通过电压具有第二电压上升宽度的升压操作Y次。第一电压上升幅度大于第二电压上升幅度，X倍少于Y倍。

29. 发明授权

US4747667A Plastic lens array 失效
标题翻译：塑料透镜阵列
公开(公告)号：US4747667A
公开(公告)日：1988-05-31
申请号：US860483
申请日：1986-05-07
申请人： Akira Tanaka , Eietsu Takahashi , Masao Tanaka , Minoru Terashima , Toshito Hara
发明人： Akira Tanaka , Eietsu Takahashi , Masao Tanaka , Minoru Terashima , Toshito Hara
IPC分类号： G03G15/00 , G02B3/00 , G02B17/00 , G02B17/08 , G02B27/18 , G02B13/26 , G02B5/04
CPC分类号： G02B17/086 , G02B17/002 , G02B17/008 , G02B3/0068
摘要： A plastic lens array including the following members which are formed integrally as one block by a plastic material; a lens array body member; a plurality of object convex lenses into which the light from an object is made incident, the object convex lenses being arranged side by side in one row along one side of the lens array body member; a plurality of image convex lenses corresponding to the object convex lenses, and being arranged side by side in a row along an opposite side of the lens array body member; a plurality of image inverting portions corresponding to the object convex lenses, each of the image inverting portions having a pair of roof surfaces which are substantially normal to each other to invert the image of an object; a first reflecting surface arranged at the backs of the object convex lenses, for totally reflecting the incident light of an object through the object convex lenses with an angle exceeding a critical angle and for guiding the reflected light of the object to a roof surface in each pair of the roof surfaces; and a second reflecting surface arranged at the backs of the image convex lenses, for totally reflecting the inverted light of an object from the other roof surface in each pair of the roof surfaces with an angle exceeding the critical angle and for guiding the reflected light of an object to the image convex lenses.
摘要翻译：一种塑料透镜阵列，包括由塑料材料一体形成的下列构件; 透镜阵列体部件; 使来自物体的光入射到其中的多个物体凸透镜，物镜凸透镜沿着透镜阵列本体构件的一侧并排布置成一列; 多个与物体凸透镜相对应的图像凸透镜，并且沿着透镜阵列本体构件的相对侧并排布置; 对应于物体凸透镜的多个图像反转部分，每个图像翻转部分具有大致相互垂直的一对顶表面，以反转物体的图像; 第一反射面，布置在物体凸透镜的后部，用于通过物体凸透镜以超过临界角的角度全反射物体的入射光，并将物体的反射光引导到每个一对屋顶表面; 以及布置在图像凸透镜的后部的第二反射表面，用于以超过临界角的角度全面地反映来自每对屋顶表面中的另一屋顶表面的物体的倒置的光，并且用于引导图像凸透镜的对象。

30. 发明授权

US4779166A Illuminating apparatus 失效
标题翻译：照明装置
公开(公告)号：US4779166A
公开(公告)日：1988-10-18
申请号：US129847
申请日：1987-12-08
申请人： Akira Tanaka , Shinpei Nagatani , Hisashi Sawada , Eietsu Takahashi , Noboru Wakatsuki , Takehisa Takoshima , Fumiaki Yamada
发明人： Akira Tanaka , Shinpei Nagatani , Hisashi Sawada , Eietsu Takahashi , Noboru Wakatsuki , Takehisa Takoshima , Fumiaki Yamada
IPC分类号： F21V8/00 , F21V7/04
CPC分类号： G02B6/0021 , G02B6/0036 , G02B6/0041 , G02B6/0061 , G02B6/0073 , G02B6/009
摘要： An illuminating apparatus which comprises a plane board composed of a transparent resin having an organic fluorescent dye incorporated therein and a light-reflecting member arranged on at least a part of the back surface of the plane board, wherein a light incident from at least a part of the end face of the plane board is emitted from at least a part of the surface of the plane board.

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