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21. 发明授权

US07888205B2 Highly scalable thin film transistor 有权
标题翻译：高度可扩展的薄膜晶体管
公开(公告)号：US07888205B2
公开(公告)日：2011-02-15
申请号：US12659480
申请日：2010-03-10
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11578
摘要： Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels.
摘要翻译： PMOS或NMOS薄膜晶体管的尺寸缩小受掺杂剂扩散的限制。在这些器件中，未掺杂或轻掺杂的沟道区被插入在重掺杂的源极和漏极区之间。当器件以非常短的栅极长度构建时，源极和漏极掺杂物将扩散到沟道中，从而潜在地短路并破坏器件。描述了一组创新，其可以以各种组合使用，以在制造PMOS或NMOS多晶薄膜晶体管期间最小化掺杂剂扩散，导致高度可缩放的薄膜晶体管。该晶体管特别适用于堆叠器件级的单片三维阵列。

22. 发明授权

US08243509B2 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 有权
标题翻译：非易失性存储单元通过增加多晶半导体材料的顺序来操作
公开(公告)号：US08243509B2
公开(公告)日：2012-08-14
申请号：US13074509
申请日：2011-03-29
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36 , G11C11/34 , G11C11/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

23. 发明申请

US20110062557A1 3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME 有权
标题翻译：具有低接触电阻的3D多晶硅二极管及其形成方法
公开(公告)号：US20110062557A1
公开(公告)日：2011-03-17
申请号：US12562079
申请日：2009-09-17
申请人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
发明人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
IPC分类号： H01L29/868 , H01L21/329
CPC分类号： H01L29/868 , H01L27/2409 , H01L27/2481 , H01L29/165 , H01L29/452 , H01L29/456 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.
摘要翻译：半导体p-i-n二极管及其形成方法在此描述。在一个方面，在被掺杂为具有一个导电性（p +或n +）和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻，这可能增加正向偏置电流。掺杂区域延伸到SiGe区域的下方，使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加，这是由于添加的SiGe区域的结果。在一个实施例中，SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配，其可以在这些二极管与 3D存储器阵列中的R / W材料。

24. 发明授权

US07177227B2 Transistor layout configuration for tight-pitched memory array lines 有权
标题翻译：紧凑型内存阵列线的晶体管布局配置
公开(公告)号：US07177227B2
公开(公告)日：2007-02-13
申请号：US11420787
申请日：2006-05-29
申请人： Christopher J. Petti , Roy E. Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher J. Petti , Roy E. Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

25. 发明授权

US08410582B2 3D polysilicon diode with low contact resistance and method for forming same 有权
标题翻译：具有低接触电阻的3D多晶硅二极管及其形成方法
公开(公告)号：US08410582B2
公开(公告)日：2013-04-02
申请号：US13479093
申请日：2012-05-23
申请人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
发明人： Abhijit Bandyopadhyay , Kun Hou , Steven Maxwell
IPC分类号： H01L29/66
CPC分类号： H01L29/868 , H01L27/2409 , H01L27/2481 , H01L29/165 , H01L29/452 , H01L29/456 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.
摘要翻译：半导体p-i-n二极管及其形成方法在此描述。在一个方面，在被掺杂为具有一个导电性（p +或n +）和与p-i-n二极管的电接触的区域之间形成SiGe区。 SiGe区域可以用于降低接触电阻，这可能增加正向偏置电流。掺杂区域延伸到SiGe区域的下方，使得其位于SiGe区域和二极管的本征区域之间。 p-i-n二极管可以由硅形成。 SiGe区域以下的掺杂区域可以用于保持反向偏置电流不增加，这是由于添加的SiGe区域的结果。在一个实施例中，SiGe被形成为使得存储器阵列中的向上指向的二极管的正向偏置电流基本上与向下指向的二极管的正向偏置电流匹配，其可以在这些二极管与 3D存储器阵列中的R / W材料。

26. 发明申请

US20110310655A1 Composition Of Memory Cell With Resistance-Switching Layers 有权
标题翻译：具有电阻切换层的存储单元的组成
公开(公告)号：US20110310655A1
公开(公告)日：2011-12-22
申请号：US13157204
申请日：2011-06-09
申请人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
发明人： Franz Kreupl , Abhijit Bandyopadhyay , Yung-Tin Chen , Chu-Chen Fu , Wipul Pemsiri Jayasekara , James Kai , Raghuveer S Makala , Peter Rabkin , George Samachisa , Jingyan Zhang
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

27. 发明申请

US20110176352A1 NONVOLATILE MEMORY CELL OPERATING BY INCREASING ORDER IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL 有权
标题翻译：通过在多晶半导体材料中增加订单来操作非易失性存储器单元
公开(公告)号：US20110176352A1
公开(公告)日：2011-07-21
申请号：US13074509
申请日：2011-03-29
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

28. 发明授权

US07054219B1 Transistor layout configuration for tight-pitched memory array lines 有权
标题翻译：紧凑型内存阵列线的晶体管布局配置
公开(公告)号：US07054219B1
公开(公告)日：2006-05-30
申请号：US11095905
申请日：2005-03-31
申请人： Christopher J. Petti , Roy E. Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher J. Petti , Roy E. Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。

29. 发明申请

US20050226067A1 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 审中-公开
标题翻译：非易失性存储单元通过增加多晶半导体材料的顺序来操作
公开(公告)号：US20050226067A1
公开(公告)日：2005-10-13
申请号：US11148530
申请日：2005-06-08
申请人： S. Herner , Abhijit Bandyopadhyay
发明人： S. Herner , Abhijit Bandyopadhyay
IPC分类号： G11C7/00 , G11C11/39 , G11C17/06 , G11C17/16 , G11C29/00 , H01L21/336 , H01L21/82 , H01L27/24 , H01L29/73 , H01L45/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

30. 发明授权

US06383855B1 High speed, low cost BICMOS process using profile engineering 失效
标题翻译：使用轮廓工程的高速，低成本BICMOS工艺
公开(公告)号：US06383855B1
公开(公告)日：2002-05-07
申请号：US09186505
申请日：1998-11-04
申请人： Minghui Gao , Haijun Zhao , Abhijit Bandyopadhyay , Pang Dow Foo
发明人： Minghui Gao , Haijun Zhao , Abhijit Bandyopadhyay , Pang Dow Foo
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and fT may be increased to 20 GHz or higher.
摘要翻译：双极互补金属氧化物半导体器件具有使用轮廓工程（使用由先进模拟确定的精确剂量和能量的多能量注入）的c-阱制造，以提供更高的c-阱注入剂量，同时产生具有相对低浓度的窄区域在集电极耗尽范围内，以避免基极集电极故障。这实现了更低的集电极串联电阻上拉频率响应，集电极薄层电阻可以低至150欧姆/平方，fT可以增加到20GHz或更高。

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