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21. 发明授权

US07559619B2 Digital lithography using real time quality control 有权
标题翻译：数字光刻使用实时质量控制
公开(公告)号：US07559619B2
公开(公告)日：2009-07-14
申请号：US11204648
申请日：2005-08-15
申请人： Steven E. Ready , William S. Wong , Scott J. H. Limb
发明人： Steven E. Ready , William S. Wong , Scott J. H. Limb
IPC分类号： B41J29/393
CPC分类号： B41J2/2139 , B81C99/0065 , B81C2201/0184 , B81C2201/0198
摘要： A digital lithography system including a droplet source (printhead) for selectively ejecting liquid droplets of a phase-change masking material, and an imaging system for capturing (generating) image data representing printed features formed by the ejected liquid droplets. The system also includes a digital control system that detects defects in the printed features, for example, by comparing the image data with stored image data. The digital control system then modifies the printed feature to correct the defect, for example, by moving the printhead over the defect and causing the printhead to eject droplets onto the defect's location. In one embodiment, a single-printhead secondary printer operates in conjunction with a multi-printhead main printer to correct defects.
摘要翻译：一种数字光刻系统，包括用于选择性地喷射相变掩模材料的液滴的液滴源（打印头）和用于捕获（产生）表示喷射液滴形成的打印特征的图像数据的成像系统。该系统还包括数字控制系统，其检测打印特征中的缺陷，例如通过将图像数据与存储的图像数据进行比较。然后，数字控制系统修改打印的特征以校正缺陷，例如通过将打印头移动到缺陷上并使打印头将液滴喷射到缺陷的位置上。在一个实施例中，单打印头二次打印机与多打印头主打印机一起操作以校正缺陷。

22. 发明授权

US07129181B2 Sub-resolution gaps generated by controlled over-etching 有权
公开(公告)号：US07129181B2
公开(公告)日：2006-10-31
申请号：US10943624
申请日：2004-09-17
申请人： JengPing Liu , Jackson H. Ho , Chinnwen Shih , Michael L. Chabinyc , William S. Wong
发明人： JengPing Liu , Jackson H. Ho , Chinnwen Shih , Michael L. Chabinyc , William S. Wong
IPC分类号： H01L21/302
CPC分类号： H01L21/76838 , B82Y30/00 , H01L21/28506 , H01L27/124
摘要： Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.

23. 发明授权

US07125495B2 Large area electronic device with high and low resolution patterned film features 有权
标题翻译：大面积电子设备具有高分辨率和低分辨率图案胶片功能
公开(公告)号：US07125495B2
公开(公告)日：2006-10-24
申请号：US11019037
申请日：2004-12-20
申请人： Robert A. Street , William S. Wong , Alberto Salleo , Michael L. Chabinyc
发明人： Robert A. Street , William S. Wong , Alberto Salleo , Michael L. Chabinyc
IPC分类号： G01D15/00
CPC分类号： H01L51/0004 , H01L51/0011 , H01L51/0021
摘要： Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes. Redundant structures are formed to further improve tolerance to misalignment, with non-optimally positioned structures removed (etched) during formation of the low resolution interconnect structures.
摘要翻译：利用两种不同的处理技术在电子设备的关键层，特别是大面积的电子设备中分别形成高分辨率特征和低分辨率特征。通过软光刻形成高分辨率特征，并且通过喷墨印刷或使用喷射印刷的蚀刻掩模形成低分辨率特征。喷墨印刷也用于缝合不对齐的结构。产生对准标记的特征是协调各种处理步骤并自动控制缝合过程。通过使用第一喷射印刷蚀刻掩模产生栅极结构来形成薄膜晶体管，使用软光刻形成源极/漏极，使用第二喷射印刷的蚀刻掩模形成互连结构，然后在源极/漏极上沉积半导体材料电极。形成冗余结构以进一步改善对未对准的容限，在形成低分辨率互连结构期间，非最佳定位的结构被去除（蚀刻）。

24. 发明授权

US07089635B2 Methods to make piezoelectric ceramic thick film arrays and elements 有权
标题翻译：制造压电陶瓷厚膜阵列和元件的方法
公开(公告)号：US07089635B2
公开(公告)日：2006-08-15
申请号：US10376544
申请日：2003-02-25
申请人： Baomin Xu , Steven A. Buhler , Michael C. Weisberg , William S. Wong , Scott E. Solberg , Karl A. Littau , John S. Fitch , Scott A. Elrod
发明人： Baomin Xu , Steven A. Buhler , Michael C. Weisberg , William S. Wong , Scott E. Solberg , Karl A. Littau , John S. Fitch , Scott A. Elrod
IPC分类号： H04R17/00
CPC分类号： B41J2/161 , B41J2/1623 , B41J2/1632 , B41J2/1634 , B41J2/1637 , B41J2/1646 , H01L41/313 , H01L41/314 , H01L41/331 , H01L2221/68368 , Y10T29/42 , Y10T29/435 , Y10T29/49128 , Y10T29/4913 , Y10T29/49133 , Y10T29/49155 , Y10T29/4981
摘要： A method of producing at least one piezoelectric element includes depositing a piezoelectric ceramic material onto a surface of a first substrate to form at least one piezoelectric element structure. Then an electrode is deposited on a surface of the at least one piezoelectric element structure. Next, the at least one piezoelectric element structure is bonded to a second substrate, the second substrate being conductive or having a conductive layer. The first substrate is then removed from the at least one piezoelectric element structure and a second side electrode is deposited on a second surface of the at least one piezoelectric element structure. A poling operation is performed to provide the at least one piezoelectric element structure with piezoelectric characteristics.
摘要翻译：制造至少一个压电元件的方法包括将压电陶瓷材料沉积到第一基板的表面上以形成至少一个压电元件结构。然后在至少一个压电元件结构的表面上沉积电极。接下来，将至少一个压电元件结构接合到第二基板，第二基板是导电的或具有导电层。然后从至少一个压电元件结构去除第一衬底，并且第二侧电极沉积在至少一个压电元件结构的第二表面上。执行极化操作以向至少一个压电元件结构提供压电特性。

25. 发明授权

US06742884B2 Apparatus for printing etch masks using phase-change materials 失效
标题翻译：使用相变材料印刷蚀刻掩模的设备
公开(公告)号：US06742884B2
公开(公告)日：2004-06-01
申请号：US09838685
申请日：2001-04-19
申请人： William S. Wong , Robert A. Street , Stephen D. White , Robert Matusiak , Raj B. Apte
发明人： William S. Wong , Robert A. Street , Stephen D. White , Robert Matusiak , Raj B. Apte
IPC分类号： E03F100
CPC分类号： B41J2/14008 , H01L21/0271 , H01L21/0332 , H01L21/0337
摘要： A method and system for masking a surface to be etched is described. A droplet source ejects droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze upon contact with the thin-film or substrate surface. The thin-film or substrate is then etched. After etching the masking material is removed.
摘要翻译：描述用于掩蔽待蚀刻表面的方法和系统。液滴源喷射掩模材料的液滴以沉积在待蚀刻的薄膜或其它衬底表面上。控制薄膜或基板表面的温度，使得液滴在与薄膜或基板表面接触时快速冷冻。然后蚀刻薄膜或衬底。蚀刻后，去除掩模材料。

26. 发明授权

US08465795B2 Annealing a buffer layer for fabricating electronic devices on compliant substrates 有权
标题翻译：退火缓冲层，用于在柔性衬底上制造电子器件
公开(公告)号：US08465795B2
公开(公告)日：2013-06-18
申请号：US12123732
申请日：2008-05-20
申请人： Rene Lujan , William S. Wong , Julia Rosolovsky Greer
发明人： Rene Lujan , William S. Wong , Julia Rosolovsky Greer
IPC分类号： B05D5/12 , B05D3/02
CPC分类号： H01L27/1218
摘要： A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.
摘要翻译：在柔性基板上形成薄膜层状电子器件的方法包括以下步骤：在柔性衬底上沉积缓冲层，将衬底和缓冲层堆叠加热至缓冲层发生塑性变形的温度，冷却堆叠，然后在塑性变形的缓冲层上形成薄膜电子器件，而不会使缓冲层进一步塑性变形。将缓冲层引起塑性变形的加热和冷却称为退火。薄膜电子器件通过一种方法形成，根据该方法，所有步骤在低于缓冲层进一步塑性变形的温度下进行。过程中的应变和跳动减少，提高柔性基板上的器件产量。可以在退火之前在缓冲层上形成任选的金属基层。

27. 发明授权

US08058113B2 Printing method for high performance electronic devices 有权
标题翻译：高性能电子设备的打印方法
公开(公告)号：US08058113B2
公开(公告)日：2011-11-15
申请号：US12901365
申请日：2010-10-08
申请人： Michael L. Chabinyc , William S. Wong
发明人： Michael L. Chabinyc , William S. Wong
IPC分类号： H01L21/84
CPC分类号： H01L51/0005 , B82Y10/00 , H01L51/0012 , H01L51/0048 , H01L51/0545 , Y10S977/723 , Y10S977/786
摘要： A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.
摘要翻译：描述了允许精确定位和取向的细长纳米结构的沉积方法。该方法涉及在载体溶液中印刷或以其它方式沉积细长的纳米结构。沉积的液滴也是细长的，通常通过图案化沉积有液滴的表面。当液滴蒸发时，控制液滴内的流体流动，使得纳米结构沉积在细长液滴的边缘或细长液滴的中心。所描述的沉积技术特别适用于形成晶体管的有源区。

28. 发明申请

US20110073840A1 RADIAL CONTACT FOR NANOWIRES 审中-公开
公开(公告)号：US20110073840A1
公开(公告)日：2011-03-31
申请号：US12571339
申请日：2009-09-30
申请人： Michael L. Chabinyc , William S. Wong , Sourobh Raychaudhuri
发明人： Michael L. Chabinyc , William S. Wong , Sourobh Raychaudhuri
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/41733 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/78696
摘要： An embodiment is a method and apparatus of radial contact using nanowires. An inner contact has a center. An outer contact surrounds the inner contact around the center and is spaced from the inner contact by a channel length. A nanowire connects the center of the inner contact and the outer contact in a rotationally invariant geometry.Another embodiment is a method and apparatus of a semiconductor device with bottom gate structure and having radial contact using nanowires. A gate electrode is deposited on a substrate. A dielectric layer is deposited on the substrate and the gate electrode. A source-drain assembly is deposited on the dielectric layer. The source-drain assembly has source and drain electrodes connected via a nanowire in a rotationally invariant geometry.Another embodiment is a method and apparatus of a semiconductor device with top gate structure and having radial contact using nanowires. An isolation barrier layer is deposited on a substrate. A source-drain assembly is deposited on the substrate and within the isolation barrier layer. The source-drain assembly has source and drain electrodes connected via a nanowire in a rotationally invariant geometry. A dielectric layer is deposited on the source-drain assembly. A gate electrode is deposited on the dielectric layer.Another embodiment is a method and apparatus of a semiconductor device having radial contact using nanowires of short lengths. Source and drain electrodes are fabricated having a contact structure with a rotationally invariant geometry. The contact structure has inner and outer contacts corresponding to the source and drain electrodes, respectively. The outer contact is spaced from the inner contact by a channel length. Wells are formed in vicinity of the contact structure. A suspension is placed in the wells. The suspension has single or multiple nanowires having a short length in a liquid. An alternating current (AC) source is applied to the contact structure to cause the single or multiple nanowires to align and connect the inner contact to the outer contact. The AC source has a first terminal connected to the inner contact and a second terminal not connected to the inner and outer contacts.

29. 发明申请

US20100252927A1 Pattern-Print Thin-Film Transistors with Top Gate Geometry 有权
标题翻译：带顶栅几何图案印刷薄膜晶体管
公开(公告)号：US20100252927A1
公开(公告)日：2010-10-07
申请号：US12817127
申请日：2010-06-16
申请人： William S. Wong , Rene A. Lujan , Eugene M. Chow
发明人： William S. Wong , Rene A. Lujan , Eugene M. Chow
IPC分类号： H01L29/45
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

30. 发明申请

US20100136757A1 METHOD FOR ALIGNING ELONGATED NANOSTRUCTURES 有权
标题翻译：用于对准延伸的纳米结构的方法
公开(公告)号：US20100136757A1
公开(公告)日：2010-06-03
申请号：US12691676
申请日：2010-01-21
申请人： Michael L. Chabinyc , William S. Wong
发明人： Michael L. Chabinyc , William S. Wong
IPC分类号： H01L21/336 , B05D5/12
CPC分类号： B82Y10/00 , H01L51/0047 , H01L51/0048 , H01L51/0525 , Y10S977/762 , Y10T428/24802
摘要： A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.
摘要翻译：描述了允许精确定位和取向的细长纳米结构的沉积方法。该方法涉及在载体溶液中印刷或以其它方式沉积细长的纳米结构。沉积的液滴也是细长的，通常通过图案化沉积有液滴的表面。当液滴蒸发时，控制液滴内的流体流动，使得纳米结构沉积在细长液滴的边缘或细长液滴的中心。所描述的沉积技术特别适用于形成晶体管的有源区。

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