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21. 发明授权

US6062133A Global planarization method and apparatus 有权
标题翻译：全局平面化方法和装置
公开(公告)号：US6062133A
公开(公告)日：2000-05-16
申请号：US287502
申请日：1999-04-07
申请人： Guy Blalock
发明人： Guy Blalock
IPC分类号： B29C43/56 , B30B1/00 , B30B15/06 , B30B5/02
CPC分类号： B29C43/56 , B30B1/003 , B30B15/061 , H01L21/68742 , H01L21/68757 , H01L21/68785 , B29C2043/561 , B29C43/32
摘要： An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or "puck" disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer, ensuring the formation of a high quality planar surface. The surface of the wafer assumes the shape of the pressing surface and is hardened in a suitable manner while under pressure to produce a globally planarized surface on the wafer. After the force is removed from the rigid plate, lift pins are slidably inserted through the rigid plate and the flexible pressing member to lift the wafer off of the surface of the flexible pressing member.
摘要翻译：一种用于在生产规模上执行晶片的可变形层的表面的全局平坦化的装置。该装置包括具有按压表面并容纳刚性板和设置在刚性板和按压表面之间的柔性按压构件或“圆盘”的腔室。具有可变形最外层的晶片被放置在柔性按压构件上，使得晶片的可变形层直接相对并且基本上平行于按压表面。将力施加到通过柔性按压构件传播的刚性板，以将晶片的可变形层压靠在按压表面上。优选地，使用波纹管布置来确保对刚性板均匀施加的力。柔性圆盘用于提供将施加的力均匀分布到晶片的自调节模式，确保形成高质量的平面表面。晶片的表面呈压制表面的形状并且在压力下以合适的方式硬化以在晶片上产生全局平坦化的表面。在从刚性板移除力之后，提升销可滑动地插入穿过刚性板和柔性按压构件以将晶片提离出柔性按压构件的表面。

22. 发明授权

US6025271A Method of removing surface defects or other recesses during the formation of a semiconductor device 失效
公开(公告)号：US6025271A
公开(公告)日：2000-02-15
申请号：US986428
申请日：1997-12-08
申请人： Bradley J. Howard , Mark E. Jost , Guy Blalock
发明人： Bradley J. Howard , Mark E. Jost , Guy Blalock
IPC分类号： H01L21/768 , H01L21/461
CPC分类号： H01L21/7684 , H01L21/76819
摘要： A method for removing a surface defect from a dielectric layer during the formation of a semiconductor device comprises the steps of forming a dielectric layer having a hole therein, the dielectric also having a surface defect resulting from a previous manufacturing step such as chemical mechanical polish, contact with another surface during production, or from a manufacturing defect. A blanket conductive layer is then formed within the hole, within the surface defect, and over the dielectric layer. The conductive layer is etched from the surface of the dielectric using an etch which removes the conductive layer at a substantially faster rate than it removes the dielectric. This etch is stopped when the level of conductive material in the plug is flush with the upper surface of the dielectric. Next, the conductive and dielectric layers are etched using a dry or plasma etch which removes the conductive and dielectric layers at about the same rate. This etch continues until the surface defect in the dielectric layer is removed, thereby forming a nonrecessed plug.

23. 发明授权

US5716873A Method for cleaning waste matter from the backside of a semiconductor wafer substrate 失效
公开(公告)号：US5716873A
公开(公告)日：1998-02-10
申请号：US643484
申请日：1996-05-06
申请人： Kirk Prall , Guy Blalock
发明人： Kirk Prall , Guy Blalock
IPC分类号： H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/28 , H01L21/312
CPC分类号： H01L21/02043 , Y02P80/30 , Y10S438/906 , Y10S438/928
摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.

24. 发明授权

US5286344A Process for selectively etching a layer of silicon dioxide on an underlying stop layer of silicon nitride 失效
标题翻译：用于选择性地蚀刻氮化硅的下伏停止层上的二氧化硅层的工艺
公开(公告)号：US5286344A
公开(公告)日：1994-02-15
申请号：US898505
申请日：1992-06-15
申请人： Guy Blalock , David S. Becker , Fred Roe
发明人： Guy Blalock , David S. Becker , Fred Roe
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/31116 , H01L21/76802
摘要： More specifically, a process is provided for etching a multilayer structure to form a predetermined etched pattern therein. The subject process comprises providing the multilayer structure having a plurality of structural layers. The structural layers of the multilayer structure comprise a silicon dioxide outer layer on an underlying silicon nitride stop layer. Then, a chemical etchant protective layer is formed on a major surface of the multilayer structure having a predetermined pattern of openings, thereby exposing areas of the silicon dioxide outer layer corresponding to the predetermined pattern of openings. The exposed areas of the silicon dioxide outer layer are then etched down to the silicon nitride stop layer, at a high SiO.sub.2 etch rate and at a high level of selectivity of the SiO.sub.2 etch rate with respect to the Si.sub.3 N.sub.4 etch rate, with a fluorinated chemical etchant system. The fluorinated chemical etchant system includes an etchant material and an additive material. The additive material comprises a fluorocarbon material in which the number of hydrogen atoms is equal to or greater than the number of fluorine atoms. The etching step forms a substantially predetermined etch pattern in the silicon dioxide outer layer in which the contact sidewalls of said SiO.sub.2 outer layer are substantially upright.
摘要翻译：更具体地，提供了用于蚀刻多层结构以在其中形成预定蚀刻图案的工艺。本发明的方法包括提供具有多个结构层的多层结构。多层结构的结构层包括在下面的氮化硅阻挡层上的二氧化硅外层。然后，在具有预定开口图案的多层结构的主表面上形成化学蚀刻剂保护层，从而暴露对应于预定图案开口的二氧化硅外层的区域。然后将二氧化硅外层的暴露区域以高SiO 2蚀刻速率和相对于Si 3 N 4蚀刻速率的SiO 2蚀刻速率的高选择性，以氟化化学品的方式蚀刻到氮化硅阻挡层蚀刻系统氟化学蚀刻剂系统包括蚀刻剂材料和添加剂材料。添加剂材料包括其中氢原子数等于或大于氟原子数的氟碳材料。蚀刻步骤在二氧化硅外层中形成基本上预定的蚀刻图案，其中所述SiO 2外层的接触侧壁基本上是直立的。

25. 发明授权

US08106438B2 Stud capacitor device and fabrication method 有权
标题翻译：螺柱电容器及其制造方法
公开(公告)号：US08106438B2
公开(公告)日：2012-01-31
申请号：US11209011
申请日：2005-08-22
申请人： Guy Blalock , Scott Meikle
发明人： Guy Blalock , Scott Meikle
IPC分类号： H01L29/94
CPC分类号： H01L28/91 , H01L28/65
摘要： The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so as to overlie the first conductive layer and fill the recess, and etching the first and second conductive layers so as to define a lower electrode within the recess. The method further comprises forming a cap layer on the lower electrode so as to overlie the first conductive layer and the filler layer and etching at least a portion of the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Subsequently, the remainder of the capacitor structure may be formed by depositing a dielectric layer on the lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.
摘要翻译：本教导涉及在基板上形成容器电容器结构的方法。在一个实施例中，该方法包括蚀刻衬底中的凹槽，在衬底上沉积第一导电层以覆盖衬底和凹部，沉积填充层以覆盖第一导电层并填充凹槽，以及蚀刻第一和第二导电层以便在凹陷内限定下电极。所述方法还包括在所述下电极上形成覆盖层，以覆盖所述第一导电层和所述填充层，并且蚀刻所述衬底的至少一部分远离所述下电极，从而至少部分隔离所述下电极。随后，电容器结构的其余部分可以通过在下电极上沉积电介质层并在电介质层上沉积第二导电层以形成上电极而形成。

26. 发明申请

US20070131247A1 Method and apparatus for surface tension control in advanced photolithography 有权
标题翻译：先进光刻中表面张力控制的方法和装置
公开(公告)号：US20070131247A1
公开(公告)日：2007-06-14
申请号：US11302293
申请日：2005-12-13
申请人： Guy Blalock
发明人： Guy Blalock
IPC分类号： C23G1/00
CPC分类号： H01L21/67034 , G03F7/422
摘要： A method and apparatus for cleaning and drying a semiconductor wafer is disclosed. Within a sealable chamber, a wafer having photoresist features thereon is spun while a cleaning fluid is applied to the top surface of the semiconductor wafer to clean off excess photoresist. A rinsing solution is applied to rinse the semiconductor wafer of any remaining impurities. To reduce stresses on the photoresist features caused by surface tension of the rinsing solution as it dries, which stresses may cause toppling of the features, the semiconductor wafer is dried in a vapor ambient within the sealable chamber. The vapor ambient, formed by combining an inert gas with a vaporized surface tension modifying fluid, produces a Marangoni effect to reduce surface tension of the rinsing solution. Optionally, to further reduce surface tension, a surfactant may be introduced into the rinsing solution and the temperature and pressure of the interior of the sealed chamber may be adjusted.
摘要翻译：公开了一种用于清洁和干燥半导体晶片的方法和装置。在可密封的腔室中，其上具有光刻胶特征的晶片被旋转，同时将清洁流体施加到半导体晶片的顶表面以清除多余的光致抗蚀剂。施加冲洗溶液以冲洗半导体晶片中任何剩余的杂质。为了减少由于冲洗溶液干燥时由表面张力引起的光致抗蚀剂特征的应力，哪些应力可能导致特征的翻倒，半导体晶片在可密封的室内的蒸汽环境中被干燥。通过将惰性气体与气化表面张力调节流体结合而形成的蒸汽环境产生马兰戈尼效应以降低冲洗溶液的表面张力。任选地，为了进一步降低表面张力，可以将表面活性剂引入冲洗溶液中，并且可以调节密封室内部的温度和压力。

27. 发明申请

US20060267472A1 Field emission tips, arrays, and devices 审中-公开
标题翻译：场发射提示，阵列和设备
公开(公告)号：US20060267472A1
公开(公告)日：2006-11-30
申请号：US11500124
申请日：2006-08-07
申请人： Guy Blalock , Sanh Tang , Zhaohui Huang
发明人： Guy Blalock , Sanh Tang , Zhaohui Huang
IPC分类号： H01J1/16 , H01J1/02 , H01J1/00
CPC分类号： H01J1/304 , H01J1/3044 , H01J31/127 , H01J2201/30446
摘要： A field emission tip includes a base with a central portion and a tapered portion. The central portion of the base includes a peripheral surface, at least a portion of which is oriented substantially vertically or perpendicularly relative to a plane in which a substrate from which the field emission tip protrudes resides. An apex may be located at an exposed end of the central portion of the base. The tapered portion of the base includes an inclined surface that extends toward the exposed end of the central portion of the base. The tapered portion of the base may be formed from material that is redeposited as the emission tip is fabricated. The apex may be formed, at least in part, from a low work function material, such as one or more of aluminum titanium silicide, titanium silicide nitride, titanium nitride, tri-chromium mono-silicon, and tantalum nitride. Field emission arrays and field emission displays that include such field emission tips are also disclosed.
摘要翻译：场发射尖端包括具有中心部分和锥形部分的基部。基部的中心部分包括外周表面，其外周表面的至少一部分相对于其中场致发射尖端突出的基底所在的平面基本垂直或垂直取向。顶点可以位于基部的中心部分的暴露端。基部的锥形部分包括朝向基部的中心部分的暴露端延伸的倾斜表面。基底的锥形部分可以由制造发射尖端时再沉积的材料形成。顶点可以至少部分地由低功函数材料形成，例如铝硅化钛，硅化钛氮化物，氮化钛，三铬单硅和氮化钽中的一种或多种。还公开了包括这种场发射尖端的场致发射阵列和场致发射显示器。

28. 发明授权

US07115509B2 Method for forming polysilicon local interconnects 有权
标题翻译：用于形成多晶硅局部互连的方法
公开(公告)号：US07115509B2
公开(公告)日：2006-10-03
申请号：US10714752
申请日：2003-11-17
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/44
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

29. 发明申请

US20060208322A1 Method and apparatus for removing adjacent conductive and non-conductive materials of a microelectronic substrate 审中-公开
标题翻译：用于去除微电子衬底的相邻导电和非导电材料的方法和装置
公开(公告)号：US20060208322A1
公开(公告)日：2006-09-21
申请号：US11413286
申请日：2006-04-28
申请人： Whonchee Lee , Scott Meikle , Guy Blalock
发明人： Whonchee Lee , Scott Meikle , Guy Blalock
IPC分类号： H01L21/20
CPC分类号： H01L21/31053 , H01L21/3212 , H01L21/32125 , H01L28/65 , H01L28/91
摘要： A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material. The hard fill material can resist penetration by conductive particles, and recessing the fill material can provide for more complete removal of the conductive material external to the aperture.
摘要翻译：一种用于从微电子衬底去除相邻的导电和非导电材料的微电子衬底和方法。在一个实施例中，微电子衬底包括具有设置在孔中的导电材料（例如铂）的孔的衬底材料（例如硼磷硅酸盐玻璃）和邻近导电的孔中的填充材料（例如磷硅玻璃）材料。填充材料可以具有约0.04GPa或更高的硬度，并且例如在从孔中去除填充材料之后，诸如电极的微电子结构可以设置在孔中。孔的外部的导电和填充材料的部分可以通过化学机械抛光填充材料，将填充材料从导电材料向内凹陷，以及电化学机械抛光导电材料来去除。硬填充材料可以抵抗导电颗粒的渗透，并且凹陷填充材料可以提供更全面地去除孔的外部的导电材料。

30. 再颁专利

USRE39194E1 Method and apparatus for controlling planarizing characteristics in mechanical and chemical-mechanical planarization of microelectronic substrates 有权
标题翻译：用于控制微电子基板的机械和化学机械平面化中的平面化特性的方法和装置
公开(公告)号：USRE39194E1
公开(公告)日：2006-07-18
申请号：US10013333
申请日：2001-12-06
申请人： Guy Blalock
发明人： Guy Blalock
IPC分类号： B24B1/00 , B24B20/00
CPC分类号： B24B37/105 , B24B21/004 , B24B37/30 , B24B49/00
摘要： A method and apparatus for mechanical and/or chemical-mechanical planarization of microelectronic substrates. In one embodiment, an apparatus for controlling the planarizing characteristics of a microelectronic substrate has a carrier that may be positioned with respect to a polishing medium of a planarizing machine to move with respect to a microelectronic substrate during planarization. The apparatus may also have a modulator with a contact element, and the modulator may be attached to the carrier to position at least a portion of a contact element in front of a leading edge of the substrate by a selected distance during planarization. In operation, the modulator causes the contact element to selectively engage a region of the planarizing surface to modulate the contour of the planarizing surface during planarization.
摘要翻译：用于微电子衬底的机械和/或化学机械平面化的方法和装置。在一个实施例中，用于控制微电子衬底的平坦化特性的装置具有可以相对于平面化机器的抛光介质定位的载体，以在平坦化期间相对于微电子衬底移动。该装置还可以具有带有接触元件的调制器，并且调制器可以附接到载体上，以在平坦化期间将接触元件的前缘的前边缘的至少一部分定位在选定距离之前。在操作中，调制器使得接触元件选择性地接合平坦化表面的区域，以在平坦化期间调制平坦化表面的轮廓。

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