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1. 发明授权

US07884925B2 Electrical and optical system and methods for monitoring erosion of electrostatic chuck edge bead materials 有权
标题翻译：用于监测静电卡盘边缘珠材料侵蚀的电气和光学系统和方法
公开(公告)号：US07884925B2
公开(公告)日：2011-02-08
申请号：US12126625
申请日：2008-05-23
申请人： Bradley J. Howard , Eric Pape , Siwen Li
发明人： Bradley J. Howard , Eric Pape , Siwen Li
IPC分类号： G01J3/30 , G01N27/04
CPC分类号： H01J37/32642 , H01J37/32935 , H01J37/32972 , H01J37/3299
摘要： A disclosed device comprises an edge bonding seal configured to be mounted to an edge bead of the electrostatic chuck. The edge bonding seal includes a monitoring layer comprised of a first material configured to either emit a species capable of being optically monitored or having an electrical resistance value capable of being monitored, or both. The edge bonding seal further includes an edge bonding layer configured to be interspersed at least between the monitoring layer and the plasma environment. The edge bonding layer is comprised of a second material susceptible to erosion due to reaction with the plasma environment and configured to expose the monitoring layer to the plasma environment upon sufficient exposure to the plasma environment.
摘要翻译：所公开的装置包括构造成安装到静电卡盘的边缘珠缘上的边缘接合密封件。边缘接合密封件包括由第一材料构成的监测层，该第一材料被配置为发射能够被光学监测的物质或具有能够被监测的电阻值，或两者。边缘接合密封件还包括边缘粘合层，其被配置为至少散布在监测层和等离子体环境之间。边缘粘合层由与等离子体环境的反应易受侵蚀的第二材料组成，并且被配置为在充分暴露于等离子体环境时将监测层暴露于等离子体环境。

2. 发明授权

US06716763B2 Method of controlling striations and CD loss in contact oxide etch 有权
公开(公告)号：US06716763B2
公开(公告)日：2004-04-06
申请号：US09991982
申请日：2001-11-26
申请人： Li Li , Bradley J. Howard
发明人： Li Li , Bradley J. Howard
IPC分类号： H01L21302
CPC分类号： G03F7/40 , G03F7/405 , H01L21/0273 , H01L21/31116 , H01L21/31144
摘要： A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

3. 发明授权

US6028763A Capacitor and method for forming a capacitor 失效
标题翻译：用于形成电容器的电容器和方法
公开(公告)号：US6028763A
公开(公告)日：2000-02-22
申请号：US61858
申请日：1998-04-17
申请人： Bradley J. Howard
发明人： Bradley J. Howard
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01G4/008 , H01G4/06
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82
摘要： A capacitor and method for forming a capacitor is disclosed and which includes providing a node to which electrical connection is to be made; forming a first layer of conductive material to a first thickness over and in electrical connection with the node; forming a second layer of insulative material to a second thickness over the first layer, the second thickness being greater than the first thickness; forming a third layer of conductive material to a third thickness over the second layer; forming the first, second and third layers into a first capacitor plate; and forming a capacitor dielectric layer and second capacitor plate operatively adjacent the first capacitor plate.
摘要翻译：公开了一种用于形成电容器的电容器和方法，其包括提供将要进行电连接的节点; 在所述节点上形成与所述节点电连接的第一厚度的第一层导电材料; 在所述第一层上形成第二厚度的第二绝缘材料层，所述第二厚度大于所述第一厚度; 在第二层上形成第三层导电材料至第三厚度; 将第一，第二和第三层形成第一电容器板; 以及形成与第一电容器板可操作地相邻的电容器电介质层和第二电容器板。

4. 发明授权

US5750441A Mask having a tapered profile used during the formation of a semiconductor device 失效
标题翻译：掩模具有在形成半导体器件期间使用的锥形轮廓
公开(公告)号：US5750441A
公开(公告)日：1998-05-12
申请号：US650723
申请日：1996-05-20
申请人： Thomas A. Figura , Bradley J. Howard
发明人： Thomas A. Figura , Bradley J. Howard
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L21/76804
摘要： A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.
摘要翻译：用于提高与下层的接触精度的方法和装置包括以下步骤：在下层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成掩模层，然后在掩模层上形成图案化的第二光致抗蚀剂层。使用第二光致抗蚀剂层作为图案对掩模层进行图案化，然后使用掩模层作为图案来对第一光致抗蚀剂层进行图案化。在第一光致抗蚀剂层中形成锥形孔，例如使用各向异性蚀刻。锥形孔具有靠近下层的底部，并且顶部远离下面的层，孔的顶部比孔的底部更宽。

5. 发明授权

US5711851A Process for improving the performance of a temperature-sensitive etch process 失效
标题翻译：用于改善温度敏感蚀刻工艺性能的方法
公开(公告)号：US5711851A
公开(公告)日：1998-01-27
申请号：US679295
申请日：1996-07-12
申请人： Guy T. Blalock , Bradley J. Howard
发明人： Guy T. Blalock , Bradley J. Howard
IPC分类号： H01L21/311 , H01L21/00
CPC分类号： H01L21/31116
摘要： The temperature of a dry etch process of a semiconductor substrate in a plasma etch chamber is controlled to maintain selectivity while also providing a high etch rate by introducing one or more cooling steps into the etch process. To maintain selectivity of the etch as well as a high rate of etch, the formation of plasma is terminated prior to exceeding a predetermined maximum temperature at at least one selected location in the chamber. The temperature at the selected location is reduced prior to the resumption of plasma flow and etching. The plasma etch is then continued, and may optionally be terminated again to permit cooling, as needed, until etching has been completed.
摘要翻译：控制等离子体蚀刻室中的半导体衬底的干蚀刻工艺的温度以保持选择性，同时通过将一个或多个冷却步骤引入到蚀刻工艺中来提供高蚀刻速率。为了保持蚀刻的选择性以及高的蚀刻速率，等离子体的形成在超过腔室中的至少一个选定位置处的预定最大温度之前终止。在等离子体流动和蚀刻恢复之前，所选位置处的温度降低。然后继续等离子体蚀刻，并且可以根据需要可选地再次终止以允许冷却，直到蚀刻完成。

6. 发明授权

US07625460B2 Multifrequency plasma reactor 有权
标题翻译：多频等离子体反应器
公开(公告)号：US07625460B2
公开(公告)日：2009-12-01
申请号：US10632628
申请日：2003-08-01
申请人： Bradley J. Howard
发明人： Bradley J. Howard
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306 , H05B31/26
CPC分类号： H01J37/32082 , H01J37/32165
摘要： A multifrequency plasma reactor includes first, second and third power generators operably coupled to at least one of an upper and lower electrode for generating power signals. The plasma reactor further includes a controller for selectively activating the power generators according to an activation profile that results in the formation of a desirable narrow gap via in a semiconductor wafer. A method of generating a plasma in the reactor for etching the semiconductor wafer is also described by way of configuring the power generators according to various activation configurations during various phases of the etching process.
摘要翻译：多频等离子体反应器包括可操作地耦合到上电极和下电极中的至少一个用于产生功率信号的第一，第二和第三发电机。等离子体反应器还包括控制器，用于根据激活曲线来选择性地激活发电机，该激活曲线导致在半导体晶片中形成期望的窄间隙。在反应器中产生用于蚀刻半导体晶片的等离子体的方法还通过在蚀刻工艺的各个阶段期间根据各种激活配置来配置发电机来描述。

7. 发明申请

US20090290145A1 ELECTRICAL AND OPTICAL SYSTEM AND METHODS FOR MONITORING EROSION OF ELECTROSTATIC CHUCK EDGE BEAD MATERIALS 有权
标题翻译：用于监测静电花边边缘材料腐蚀的电气和光学系统及方法
公开(公告)号：US20090290145A1
公开(公告)日：2009-11-26
申请号：US12126625
申请日：2008-05-23
申请人： Bradley J. Howard , Eric Pape , Siwen Li
发明人： Bradley J. Howard , Eric Pape , Siwen Li
IPC分类号： G01N21/63
CPC分类号： H01J37/32642 , H01J37/32935 , H01J37/32972 , H01J37/3299
摘要： A disclosed device comprises an edge bonding seal configured to be mounted to an edge bead of the electrostatic chuck. The edge bonding seal includes a monitoring layer comprised of a first material configured to either emit a species capable of being optically monitored or having an electrical resistance value capable of being monitored, or both. The edge bonding seal further includes an edge bonding layer configured to be interspersed at least between the monitoring layer and the plasma environment. The edge bonding layer is comprised of a second material susceptible to erosion due to reaction with the plasma environment and configured to expose the monitoring layer to the plasma environment upon sufficient exposure to the plasma environment.
摘要翻译：所公开的装置包括构造成安装到静电卡盘的边缘珠缘上的边缘接合密封件。边缘接合密封件包括由第一材料构成的监测层，该第一材料被配置为发射能够被光学监测的物质或具有能够被监测的电阻值，或两者。边缘接合密封件还包括边缘粘合层，其被配置为至少散布在监测层和等离子体环境之间。边缘粘合层由与等离子体环境的反应易受侵蚀的第二材料组成，并且被配置为在充分暴露于等离子体环境时将监测层暴露于等离子体环境。

8. 发明授权

US07615164B2 Plasma etching methods and contact opening forming methods 失效
标题翻译：等离子体蚀刻方法和接触开口形成方法
公开(公告)号：US07615164B2
公开(公告)日：2009-11-10
申请号：US10875330
申请日：2004-06-23
申请人： Bradley J. Howard , Max F. Hineman
发明人： Bradley J. Howard , Max F. Hineman
IPC分类号： H01L21/302
CPC分类号： H01L21/31116
摘要： The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.
摘要翻译：本发明包括蚀刻和接触开口形成方法。在一个实施方案中，等离子体蚀刻方法包括提供底部供电的等离子体室，其包括可在不同的第一和第二频率下供电的等离子体产生电极，其中第一频率低于第二频率。衬底位于电极上方。在基板上产生等离子体，其中电极以第一频率的第一施加功率和第二频率的第二施加功率产生。第一施加功率与第二施加功率的比率为0至0.25或至少6.0。用等离子体从衬底蚀刻材料。

9. 发明授权

US07122480B2 Method of plasma etching a substrate 有权
标题翻译：等离子体蚀刻基板的方法
公开(公告)号：US07122480B2
公开(公告)日：2006-10-17
申请号：US10969568
申请日：2004-10-21
申请人： Li Li , Bradley J. Howard
发明人： Li Li , Bradley J. Howard
IPC分类号： H01L21/3065
CPC分类号： G03F7/40 , G03F7/405 , H01L21/0273 , H01L21/31116 , H01L21/31144
摘要： A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.
摘要翻译：公开了一种用于控制等离子体蚀刻方法中的条纹和CD损耗的方法。在蚀刻工艺期间，待蚀刻的半导体材料的衬底首先在低功率冲击下暴露于等离子体，然后暴露于传统的高功率冲击。已经发现CD损耗减少约400埃，并且在接触孔中形成的条纹减小。

10. 发明授权

US06524875B2 Method for manufacturing tapered opening using an anisotropic etch during the formation of a semiconductor device 有权
标题翻译：在形成半导体器件期间使用各向异性蚀刻制造锥形开口的方法
公开(公告)号：US06524875B2
公开(公告)日：2003-02-25
申请号：US10015260
申请日：2001-12-11
申请人： Thomas A. Figura , Bradley J. Howard
发明人： Thomas A. Figura , Bradley J. Howard
IPC分类号： A01L2100
CPC分类号： H01L21/76804
摘要： A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.
摘要翻译：用于提高与下层的接触精度的方法和装置包括以下步骤：在下层上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成掩模层，然后在掩模层上形成图案化的第二光致抗蚀剂层。使用第二光致抗蚀剂层作为图案对掩模层进行图案化，然后使用掩模层作为图案来对第一光致抗蚀剂层进行图案化。在第一光致抗蚀剂层中形成锥形孔，例如使用各向异性蚀刻。锥形孔具有靠近下层的底部，并且顶部远离下面的层，孔的顶部比孔的底部更宽。

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