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1. 发明授权

US07115509B2 Method for forming polysilicon local interconnects 有权
标题翻译：用于形成多晶硅局部互连的方法
公开(公告)号：US07115509B2
公开(公告)日：2006-10-03
申请号：US10714752
申请日：2003-11-17
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/44
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

2. 发明申请

US20050285148A1 Memory with polysilicon local interconnects 审中-公开
标题翻译：具有多晶硅局部互连的存储器
公开(公告)号：US20050285148A1
公开(公告)日：2005-12-29
申请号：US11217739
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336 , H01L21/768 , H01L21/8247 , H01L23/48 , H01L27/115 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

3. 发明授权

US6080675A Method for cleaning waste matter from the backside of a semiconductor wafer substrate 有权
标题翻译：从半导体晶片基板的背面清洗废物的方法
公开(公告)号：US6080675A
公开(公告)日：2000-06-27
申请号：US344435
申请日：1999-06-25
申请人： Kirk Prall , Guy Blalock
发明人： Kirk Prall , Guy Blalock
IPC分类号： H01L21/306 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/02043 , Y02P80/30 , Y10S438/906 , Y10S438/928
摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a covet layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.
摘要翻译：一种在晶片上制造半导体器件的方法，该半导体器件具有正面和背面的衬底，以及在衬底的背面积聚废物。在本发明的方法中，在用于制造晶片上的部件的工艺的正常涂覆步骤中，在前侧上沉积蜂窝层。覆盖层提供用于制造晶片正面上的部件的工艺中使用的材料，并在前侧形成阻挡层。通过用合适的蚀刻剂从晶片的背面蚀刻废物，或者通过化学机械平坦化（“CMP”）工艺平坦化晶片的背面，从晶片的背面去除废物。在去除步骤期间，覆盖层保护前侧，并且当废物从晶片的背面移除时，前侧上的任何装置特征不被损坏。由于覆盖层在用于制造晶片上的部件的工艺的正常涂覆步骤中沉积，所以不管废物是否从晶片上移除，都被沉积。

4. 发明授权

US5958796A Method for cleaning waste matter from the backside of a semiconductor wafer substrate 失效
标题翻译：从半导体晶片基板的背面清洗废物的方法
公开(公告)号：US5958796A
公开(公告)日：1999-09-28
申请号：US915193
申请日：1997-08-20
申请人： Kirk Prall , Guy Blalock
发明人： Kirk Prall , Guy Blalock
IPC分类号： H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/28 , H01L21/31 , H01L21/3205
CPC分类号： H01L21/02043 , Y02P80/30 , Y10S438/906 , Y10S438/928
摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.
摘要翻译：一种在晶片上制造半导体器件的方法，该半导体器件具有正面和背面的衬底，以及在衬底的背面积聚废物。在本发明的方法中，在用于在晶片上制造部件的工艺的正常涂覆步骤中，在正面上沉积覆盖层。覆盖层提供用于制造晶片正面上的部件的工艺中使用的材料，并在前侧形成阻挡层。通过用合适的蚀刻剂从晶片的背面蚀刻废物，或者通过化学机械平坦化（“CMP”）工艺平坦化晶片的背面，从晶片的背面去除废物。在去除步骤期间，覆盖层保护前侧，并且当废物从晶片的背面移除时，前侧上的任何装置特征不被损坏。由于覆盖层在用于制造晶片上的部件的工艺的正常涂覆步骤中沉积，所以不管废物是否从晶片上移除，都被沉积。

5. 发明申请

US20060009035A1 Method for forming polysilicon local interconnects 审中-公开
公开(公告)号：US20060009035A1
公开(公告)日：2006-01-12
申请号：US11218099
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/44
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

6. 发明申请

US20060008989A1 Method for forming an array with polysilicon local interconnects 有权
公开(公告)号：US20060008989A1
公开(公告)日：2006-01-12
申请号：US11217946
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

7. 发明授权

US06448656B1 System including a memory device having a semiconductor connection with a top surface having an enlarged recess 有权
标题翻译：该系统包括具有半导体连接的存储器件，顶部表面具有扩大的凹槽
公开(公告)号：US06448656B1
公开(公告)日：2002-09-10
申请号：US09583679
申请日：2000-05-31
申请人： Fernando Gonzalez , Guy Blalock , Kirk Prall
发明人： Fernando Gonzalez , Guy Blalock , Kirk Prall
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L23/485 , H01L23/5226 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.
摘要翻译：形成连接的方法包括沉积下导体的步骤。电介质层沉积在下导体上，电介质层具有与下导体相邻的下表面，并具有上表面。形成在电介质层的上表面和下表面之间延伸的开口。导电插塞沉积在开口内，插头具有接近电介质层的上表面的上表面。上表面具有插头的上表面与电介质层相邻的边缘。在插头的上表面的边缘附近形成凹部，凹部延伸到插塞和介电层两者中。最后，在电介质层的上表面和插头的上表面上沉积上导体。还公开了如此形成的连接。

8. 发明授权

US5892285A Semiconductor connection with a top surface having an enlarged recess 失效
标题翻译：与具有扩大凹部的顶表面的半导体连接
公开(公告)号：US5892285A
公开(公告)日：1999-04-06
申请号：US801345
申请日：1997-02-19
申请人： Fernando Gonzalez , Guy Blalock , Kirk Prall
发明人： Fernando Gonzalez , Guy Blalock , Kirk Prall
IPC分类号： H01L23/485 , H01L23/522 , H01L23/528 , H01L23/535 , H01L23/48 , H01L23/52
CPC分类号： H01L23/5283 , H01L23/485 , H01L23/5226 , H01L23/535 , H01L2924/0002
摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.
摘要翻译：形成连接的方法包括沉积下导体的步骤。电介质层沉积在下导体上，电介质层具有与下导体相邻的下表面，并具有上表面。形成在电介质层的上表面和下表面之间延伸的开口。导电插塞沉积在开口内，插头具有接近电介质层的上表面的上表面。上表面具有插头的上表面与电介质层相邻的边缘。在插头的上表面的边缘附近形成凹部，凹部延伸到插塞和介电层两者中。最后，在电介质层的上表面和插头的上表面上沉积上导体。还公开了如此形成的连接。

9. 发明授权

US07569468B2 Method for forming a floating gate memory with polysilicon local interconnects 失效
标题翻译：用于形成具有多晶硅局部互连的浮动栅极存储器的方法
公开(公告)号：US07569468B2
公开(公告)日：2009-08-04
申请号：US11217624
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

10. 发明申请

US20060008963A1 Method for forming polysilicon local interconnects 审中-公开
公开(公告)号：US20060008963A1
公开(公告)日：2006-01-12
申请号：US11217950
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

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