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21. 发明申请

US20070015330A1 Metal/semiconductor/metal (MSM) back-to-back Schottky diode 有权
标题翻译：金属/半导体/金属（MSM）背对背肖特基二极管
公开(公告)号：US20070015330A1
公开(公告)日：2007-01-18
申请号：US11435669
申请日：2006-05-17
申请人： Tingkai Li , Sheng Hsu , David Evans
发明人： Tingkai Li , Sheng Hsu , David Evans
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

22. 发明申请

US20070238246A1 Resistance random access memory devices and method of fabrication 有权
标题翻译：电阻随机存取存储器件及其制造方法
公开(公告)号：US20070238246A1
公开(公告)日：2007-10-11
申请号：US11403020
申请日：2006-04-11
申请人： Tingkai Li , Sheng Hsu , David Evans
发明人： Tingkai Li , Sheng Hsu , David Evans
IPC分类号： H01L21/336
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616 , H01L45/1641
摘要： A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size and amorphous PCMO structure. A top electrode is formed on the PCMO layer.
摘要翻译：制造RRAM的方法包括制备衬底并形成底部电极或衬底。使用MOCVD或液体MOCVD将PCMO层沉积在底部电极上，随后进行后退火处理。沉积的PCMO薄膜具有结晶的PCMO结构或纳米尺寸和无定形PCMO结构。顶部电极形成在PCMO层上。

23. 发明申请

US20050014296A1 MOCVD OF TIO2 THIN FILM FOR USE AS FERAM H2 PASSIVATION LAYER 失效
标题翻译： MOCVD OF TIO2薄膜用作FERAM H2钝化层
公开(公告)号：US20050014296A1
公开(公告)日：2005-01-20
申请号：US10621863
申请日：2003-07-16
申请人： Tingkai Li , Wei Pan , Robert Barrowcliff , David Evans , Sheng Hsu
发明人： Tingkai Li , Wei Pan , Robert Barrowcliff , David Evans , Sheng Hsu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/28291 , H01L21/31604 , H01L27/11585 , H01L27/1159 , H01L28/57 , H01L29/6684
摘要： A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0
摘要翻译：在FeRAM中形成H 2钝化层的方法包括制备硅衬底; 在大马士革结构上沉积一层TiOx薄膜，其中0

24. 发明申请

US20050141269A1 Electrically programmable resistance cross point memory circuit 审中-公开
标题翻译：电可编程电阻交叉点存储电路
公开(公告)号：US20050141269A1
公开(公告)日：2005-06-30
申请号：US11066708
申请日：2005-02-24
申请人： Sheng Hsu , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei-Wei Zhuang
IPC分类号： H01L27/115 , G11C11/15 , G11C11/56 , G11C13/00 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/24 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15 , G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
摘要翻译：提供了电阻式交叉点存储器件以及制造和使用方法。存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。提供存储器电路以帮助编程和读出位区域。

25. 发明申请

US20050136602A1 Dual-trench isolated crosspoint memory array 有权
标题翻译：双沟隔离交叉点存储器阵列
公开(公告)号：US20050136602A1
公开(公告)日：2005-06-23
申请号：US11039536
申请日：2005-01-19
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： H01L21/76 , G11C13/00 , H01L21/3205 , H01L21/8246 , H01L23/52 , H01L27/10 , H01L27/105 , H01L27/24 , H01L43/08 , H01L29/02 , H01L21/336 , H01L21/4763 , H01L47/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/101 , H01L27/24
摘要： A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.
摘要翻译：已经提供了存储器阵列双沟槽隔离结构及其形成方法。该方法包括：形成p掺杂硅（p-Si）衬底; 形成覆盖p-Si衬底的n掺杂（n +）Si层; 在形成n + Si位线之前，形成覆盖n + Si层的p + Si层; 形成覆盖p +层的氮化硅层; 形成覆盖所述氮化硅层的顶部氧化物层; 执行顶部氧化物层，氮化硅层，p + Si层和n + Si层的一部分的第一选择性蚀刻，以在位线之间形成n + Si位线和位线沟槽; 形成覆盖多个n掺杂硅（n + Si）位线的金属底部电极阵列，具有中间p掺杂（p +）Si区域; 形成与所述n + Si位线正交并覆盖与所述底部电极相邻并分离所述p + Si区域的多个字线氧化物隔离结构; 形成与n + Si位线正交的多个顶部电极字线，覆盖在底部电极上的插入式存储电阻材料; 并且在字线附近形成氧化物填充的字线沟槽。

26. 发明申请

US20050083757A1 Cross-point resistor memory array 有权
标题翻译：交叉点电阻存储器阵列
公开(公告)号：US20050083757A1
公开(公告)日：2005-04-21
申请号：US10971204
申请日：2004-10-21
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , G11C7/00
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/72 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
摘要翻译：提供了电阻式交叉点存储器件，以及制造和使用方法。存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。电阻交叉点存储器件通过在衬底内掺杂一行极性形成，然后将相反极性的线的掺杂区域形成二极管。然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

27. 发明申请

US20060246606A1 Self-aligned cross point resistor memory array 有权
标题翻译：自对准交叉点电阻存储器阵列
公开(公告)号：US20060246606A1
公开(公告)日：2006-11-02
申请号：US11120385
申请日：2005-05-02
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
IPC分类号： H01L21/8234
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.
摘要翻译：制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

28. 发明申请

US20050158994A1 PCMO spin-coat deposition 有权
标题翻译： PCMO旋涂沉积
公开(公告)号：US20050158994A1
公开(公告)日：2005-07-21
申请号：US10759468
申请日：2004-01-15
申请人： Wei-Wei Zhuang , Lisa Stecker , Gregory Stecker , Sheng Hsu
发明人： Wei-Wei Zhuang , Lisa Stecker , Gregory Stecker , Sheng Hsu
IPC分类号： C01G45/00 , H01L21/28 , H01L23/62 , H01L27/10 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1683
摘要： A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.
摘要翻译：提供了一种用于消除空隙的Pr 1-X C 3 Mn 3 O 3（PCMO）旋涂沉积方法，以及无空隙 PCMO薄膜结构。该方法包括：用表面形成包括贵金属的基底; 形成相对于衬底表面正常的特征，例如通孔或沟槽; 用乙酸旋涂底物; 用第一种低浓度的PCMO溶液旋涂底物; 以第二浓度的PCMO溶液旋涂底物，其具有比第一浓度更高浓度的PCMO; 烘烤和RTA退火（重复1〜5次）; 后退火; 并且在PCMO膜和下面的衬底表面之间形成具有无空隙界面的PCMO膜。 PCMO溶液的第一浓度的PCMO浓度范围为0.01至0.1摩尔（M）。 PCMO溶液的第二浓度的PCMO浓度范围为0.2-0.5M。

29. 发明申请

US20050054138A1 Method of fabricating trench isolated cross-point memory array 有权
公开(公告)号：US20050054138A1
公开(公告)日：2005-03-10
申请号：US10971263
申请日：2004-10-21
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , H01L21/00
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

30. 发明申请

US20060094187A1 Method of changing an electrically programmable resistance cross point memory bit 有权
标题翻译：改变电可编程电阻交叉点存储器位的方法
公开(公告)号：US20060094187A1
公开(公告)日：2006-05-04
申请号：US11066592
申请日：2005-02-24
申请人： Sheng Hsu , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei-Wei Zhuang
IPC分类号： H01L21/336
CPC分类号： G11C11/15 , G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
摘要翻译：提供了电阻式交叉点存储器件以及制造和使用方法。存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。提供存储器电路以帮助编程和读出位区域。

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