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    • 22. 发明申请
    • IrOx nanowire neural sensor
    • IrOx纳米线神经传感器
    • US20080299381A1
    • 2008-12-04
    • US11809959
    • 2007-06-04
    • Fengyan ZhangBruce D. UlrichWei GaoSheng Teng Hsu
    • Fengyan ZhangBruce D. UlrichWei GaoSheng Teng Hsu
    • B32B3/26B05D5/12
    • A61N1/0543B82Y15/00B82Y30/00Y10T29/49128Y10T29/4913Y10T29/49165Y10T29/49167Y10T29/49169Y10T428/24998
    • An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
    • 提供氧化铱(IrOx)纳米线神经传感器阵列及相关制造方法。 该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。 基板可以是诸如Si,SiO 2,石英,玻璃或聚酰亚胺的材料,并且导电层是诸如ITO,SnO 2,ZnO,TiO 2,掺杂的ITO,掺杂的SnO 2,掺杂的ZnO,掺杂的TiO 2,TiN, TaN,Au,Pt或Ir。 电介质层被选择性地湿蚀刻,与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面,并且可以被成形为圆形,矩形或椭圆形。
    • 24. 发明授权
    • Electroluminescent device
    • 电致发光器件
    • US07208768B2
    • 2007-04-24
    • US10836669
    • 2004-04-30
    • Yoshi OnoWei GaoJohn F. Conley, Jr.Osamu NishioKeizo Sakiyama
    • Yoshi OnoWei GaoJohn F. Conley, Jr.Osamu NishioKeizo Sakiyama
    • H01L27/15
    • H01L33/28H01L33/18H01L33/34Y10S977/95
    • A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II–VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.
    • 提供了形成电致发光器件的方法。 该方法包括:提供IV型半导体材料基板; 在衬底中形成p + / n +结,通常形成多个交错的p + / n +结; 并且形成覆盖衬底中的p + / n +结的电致发光层。 IV型半导体材料基板可以是Si,C,Ge,SiGe或SiC。 例如,衬底可以是绝缘体上的硅(SOI),玻璃上的体积Si,Si或塑料上的Si。 电致发光层可以是诸如纳米晶体Si,纳米晶体Ge,荧光聚合物或诸如ZnO,ZnS,ZnSe,CdSe和CdS的II-VI族材料的材料。 在一些方面,所述方法还包括形成介于基片和电致发光层之间的绝缘膜。 另一方面,该方法包括形成覆盖电致发光层的导电电极。
    • 27. 发明申请
    • Wide wavelength range silicon electroluminescence device
    • 宽波长范围的硅电致发光器件
    • US20060180816A1
    • 2006-08-17
    • US11058505
    • 2005-02-14
    • Tingkai LiWei GaoYoshi OnoSheng Hsu
    • Tingkai LiWei GaoYoshi OnoSheng Hsu
    • H01L29/26
    • H05B33/145
    • A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.
    • 提供一种用于形成用于发射短波长的光的Si电致发光(EL)装置的方法。 该方法包括:提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物(SRSO)层,其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。 通常,SRSO的Si浓度范围为5〜40%。 在一个方面,使用DC溅射工艺形成SRSO层。 另一方面,SRSO形成步骤包括在沉积SRSO之后的快速热退火(RTA)工艺。 同样地,可以在SRSO层沉积之后进行热氧化或等离子体氧化。 响应于上述沉积,退火和氧化过程,Si纳米晶体的尺寸减小。
    • 30. 发明授权
    • Plating or coating method for producing metal-ceramic coating on a substrate
    • 在基板上制造金属陶瓷涂层的电镀或涂布方法
    • US09562302B2
    • 2017-02-07
    • US13381487
    • 2010-06-29
    • Wei GaoWeiwei Chen
    • Wei GaoWeiwei Chen
    • C23C18/16C25D15/02C23C18/31C25D21/14C25D3/12C25D3/56
    • C25D15/02C23C18/1637C23C18/1662C23C18/31C25D3/12C25D3/562C25D21/14
    • A method for producing a metal-ceramic composite coating with increased hardness on a substrate includes adding a sol of a ceramic phase to the plating solution or electrolyte. The sol may be added prior to and/or during the plating or coating and at a rate of sol addition controlled to be sufficiently low that nanoparticles of the ceramic phase form directly onto or at the substrate and/or that the metal-ceramic coating forms on the substrate with a predominantly crystalline structure and/or to substantially avoid formation of nanoparticles of the ceramic phase, and/or agglomeration of particles of the ceramic phase, in the plating solution or electrolyte. The ceramic phase may be a single or mixed oxide, carbide, nitride, silicate, boride of Ti, W, Si, Zr, Al, Y, Cr, Fe, Pb, Co, or a rare earth element. The coating, other than the ceramic phase may comprise Ni, Ni—P, Ni—W—P, Ni—Cu—P, Ni—B, Cu, Ag, Au, Pd.
    • 在基板上制造硬度高的金属 - 陶瓷复合涂层的方法包括将陶瓷相的溶胶添加到电镀液或电解液中。 可以在电镀或涂覆之前和/或期间将溶胶加入,并以溶胶添加速率控制为足够低,使得陶瓷相的纳米颗粒直接形成在基底上和/或在基底上和/或金属 - 陶瓷涂层形成 在具有主要结晶结构的基底上和/或基本上避免在电镀溶液或电解质中形成陶瓷相的纳米颗粒和/或陶瓷相颗粒的聚集。 陶瓷相可以是Ti,W,Si,Zr,Al,Y,Cr,Fe,Pb,Co或稀土元素的单一或混合氧化物,碳化物,氮化物,硅酸盐,硼化物。 陶瓷相以外的涂层可以包括Ni,Ni-P,Ni-W-P,Ni-Cu-P,Ni-B,Cu,Ag,Au,Pd。