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21. 发明专利

JP2012019188A Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2012019188A
公开(公告)日：2012-01-26
申请号：JP2010275477
申请日：2010-12-10
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/046 , H01L29/0619 , H01L29/0623 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/49 , H01L29/66068 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To improve breakdown voltage characteristics of a semiconductor device.SOLUTION: A semiconductor device 100 comprises a termination area 107 surrounding a cell area 105. In the cell area 105, main trenches 113 are formed. In the termination area 107, termination trenches 161 to 163 that surround the cell area 105 are formed. The termination trench 161 is located at the innermost peripheral side of the termination trenches. A body region 141 is laminated on a surface of a drift region 112. The main trenches 113 reach the drift region 112, and have a gate electrode 122 formed therein. The termination trench 161 reaches the drift region 112. The sidewall and the bottom surface of the termination trench 161 are coated with an oxide film 171. The surface of the oxide film 171 coating the bottom surface of the termination trench 161 is coated with a buried electrode 124. A gate voltage is applied to the buried electrode 124.
摘要翻译：要解决的问题：提高半导体器件的击穿电压特性。解决方案：半导体器件100包括围绕单元区域105的终止区域107.在单元区域105中，形成主沟槽113。在终端区域107中，形成围绕单元区域105的终端沟槽161至163。终端沟槽161位于终端沟槽的最内侧。主体区域141层叠在漂移区域112的表面上。主沟槽113到达漂移区域112，并且在其中形成栅电极122。终端沟槽161到达漂移区域112.终端沟槽161的侧壁和底表面涂覆有氧化膜171.覆盖终端沟槽161的底表面的氧化膜171的表面涂覆有埋置电极124.栅极电压施加到埋入电极124.版权所有：（C）2012，JPO＆INPIT

22. 发明专利

JP2011253837A Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2011253837A
公开(公告)日：2011-12-15
申请号：JP2010124604
申请日：2010-05-31
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： SUZUKI NAOHIRO , MATSUKI HIDEO , SUGIMOTO MASAHIRO , TAKATANI HIDESHI , MORIMOTO ATSUSHI , ISHIKAWA TAKESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/66068 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide an SiC semiconductor device in which on-resistance is more reduced.SOLUTION: Each of p-type deep layers 10 has a layout where the p-type layer is divided into a plurality portions in a direction intersecting with a trench 6. Thereby, a current flowing range can be expanded even within an ntype drift layer 2 between the divided deep layers 10, so that more current can be flown between a source and a drain. Accordingly, the on-resistance of an SiC semiconductor device can be more reduced than the conventional ones.
摘要翻译：要解决的问题：提供一种其中更加降低导通电阻的SiC半导体器件。解决方案：每个p型深层10具有其中p型层在与沟槽6相交的方向上分成多个部分的布局。因此，电流流动范围甚至可以在n 在分开的深层10之间的 - / SP>类型漂移层2，使得可以在源极和漏极之间流动更多的电流。因此，与现有技术相比，可以进一步降低SiC半导体器件的导通电阻。版权所有（C）2012，JPO＆INPIT

23. 发明专利

JP2011168453A Method for producing silicon carbide substrate 有权
标题翻译：生产碳化硅基材的方法
公开(公告)号：JP2011168453A
公开(公告)日：2011-09-01
申请号：JP2010034669
申请日：2010-02-19
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , KITO YASUO , YAMAMOTO KENSAKU , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO ATSUSHI , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： C30B29/36 , C30B23/06 , H01L21/20 , H01L21/265
CPC分类号： H01L21/02529 , C30B29/36 , C30B33/02 , H01L21/02378 , H01L21/02658 , H01L21/02667 , H01L29/66068
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a SiC substrate, by which the production process can be simplified and the presence of a screw dislocation in a surface layer can be suppressed. SOLUTION: The production method includes: a step of preparing a defect-containing substrate 2 comprising silicon carbide, having a major surface and a back surface as the opposite face to the major surface, and including a screw dislocation 1 in a surface layer 2a; a first external force application step of applying an external force to the major surface of the defect-containing substrate 2 to decrease crystallinity of the surface layer 2a; and a first heat treatment step of recovering the crystallinity of the surface layer 2a by heat treating the defect-containing substrate 2 after the external force application step. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种SiC基板的制造方法，能够简化制造工序，能够抑制表面层的螺旋位错的存在。解决方案：制备方法包括：制备含有主要表面和后表面作为主表面的相对面的碳化硅的含缺陷基材2的步骤，在表面上包括螺旋位错1 层2a; 第一外力施加步骤，向所述含缺陷的衬底2的主表面施加外力以降低表面层2a的结晶度; 以及第一热处理步骤，通过在外力施加步骤之后热处理含缺陷的基板2来恢复表面层2a的结晶度。版权所有（C）2011，JPO＆INPIT

24. 发明专利

JP2011187708A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011187708A
公开(公告)日：2011-09-22
申请号：JP2010051794
申请日：2010-03-09
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKATANI HIDESHI
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0653 , H01L29/0661 , H01L29/1095 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To make the space of a termination domain small while improving a breakdown voltage. SOLUTION: The semiconductor device 10 has an element domain 40 and the termination domain 50 surrounding the element domain. The element domain 40 and termination domain 50 each have a drift region 18 of a second conductivity type. In the element domain 40, a gate trench 38 is provided. In the termination domain 50, a termination trench 22 making one round outside the element domain is provided. At a bottom portion of the gate trench 38, a diffusion domain of a first conductivity type is not formed which has its periphery surrounded with a drift region 18, and at a bottom portion of the termination trench 22, a floating region 20 of the first conductivity type is formed which has its periphery surrounded with the drift region 18. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了使终端域的空间小，同时提高击穿电压。解决方案：半导体器件10具有元件结构域40和围绕元件结构域的终止域50。元件区域40和端接区域50各自具有第二导电类型的漂移区域18。在元件区域40中，设置有栅极沟槽38。在终端域50中，提供了在元件域外形成一个圆的端接沟槽22。在栅极沟槽38的底部，没有形成第一导电类型的扩散区域，其周边被漂移区域18包围，并且在终端沟槽22的底部，第一导电类型的浮动区域20 形成导电类型，其周边被漂移区域18包围。版权所有（C）2011，JPO＆INPIT

25. 发明专利

JP2011086746A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011086746A
公开(公告)日：2011-04-28
申请号：JP2009238006
申请日：2009-10-15
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKATANI HIDESHI
IPC分类号： H01L29/78 , H01L29/06
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein breakdown voltage does not decrease easily, and the area of element region can be enlarged. SOLUTION: On the semiconductor substrate 12 of the semiconductor device 10, formed are: a first active region 14 in which a semiconductor element is formed; a second active region 16 in which a semiconductor element is formed; and an inactive region in which a gate pad 18 is formed. In the plan view of the semiconductor substrate 12, (a) the first active region 14 and the second active region 16 are formed in rectangular shape, (b) the gate pad 18 and the second active region 16 are arranged side by side in the y direction, (c) the gate pad 18 and the second active region 16 are arranged side by side in the x direction for the first active region 14, and (d) the lengths in the y direction of the gate pad 18 and the second active region 16 are set shorter than the length in the y direction of the first active region 14. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种其中击穿电压不容易降低的半导体器件，并且可以扩大元件区域的面积。解决方案：在半导体器件10的半导体衬底12上形成有形成半导体元件的第一有源区14; 形成半导体元件的第二有源区16; 以及形成栅极焊盘18的无效区域。在半导体基板12的平面图中，（a）第一有源区域14和第二有源区域16形成为矩形形状，（b）栅极焊盘18和第二有源区域16并排配置在 y方向，（c）栅极焊盘18和第二有源区域16在第一有源区域14的x方向上并排布置，以及（d）栅极焊盘18和第二有源区域16的y方向上的长度有源区域16被设置为比第一有源区域14的y方向上的长度短。版权所有：（C）2011，JPO＆INPIT

26. 发明专利

JP2010109076A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010109076A
公开(公告)日：2010-05-13
申请号：JP2008278445
申请日：2008-10-29
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKATANI HIDESHI
IPC分类号： H01L27/04 , H01L29/417 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To suppress variation in current sense ratio of a semiconductor device to ambient temperature without imposing large restrictions on the design of the semiconductor device.
SOLUTION: The semiconductor device has a main element region having a plurality of function cells and a sense element region having function cells less than those of the main element region. A second electrode 81 of the main element region includes a main region 85a to which main wiring is connected, a Kelvin terminal region 86a to which Kelvin wiring is connected, and a high-resistance region 87a formed between the main region and Kelvin terminal region and increasing the electric resistance between the main region and Kelvin region. The resistance temperature coefficient of the high-resistance region 87a is set smaller than the resistance temperature coefficient of the function cells.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了抑制半导体器件的电流感测比率与环境温度的变化，而不会对半导体器件的设计施加大的限制。解决方案：半导体器件具有具有多个功能单元的主元件区域和具有小于主元件区域的功能单元的感测元件区域。主元件区域的第二电极81包括连接有主布线的主区域85a，连接有开尔文布线的开尔文端子区域86a和形成在主区域和开尔文端子区域之间的高电阻区域87a，以及增加主区域和开尔文区域之间的电阻。高电阻区域87a的电阻温度系数被设定为小于功能单元的电阻温度系数。版权所有（C）2010，JPO＆INPIT

27. 发明专利

JP2010062361A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010062361A
公开(公告)日：2010-03-18
申请号：JP2008226942
申请日：2008-09-04
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKATANI HIDESHI
IPC分类号： H01L29/06 , H01L21/822 , H01L27/04 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a breakdown voltage from decreasing in the semiconductor device having a plurality of trenches for retaining a breakdown voltage formed in the peripheral region. SOLUTION: The semiconductor device 100 includes: an n type semiconductor substrate 15 divided into a center region 18A and a peripheral region 18B surrounding the outside of the center region 18A; a p type body region 14 formed from the center region 18A to the peripheral region 18B; the plurality of termination trenches 12a-12c formed in the peripheral region 18B; a dividing trench 12d; and p type diffusion regions 6a-6d formed in a range surrounding the bottom of each trench. The termination trenches 12a-12c are disposed at an interval, where a depletion layer is connected in discontinuity of a circuit element. The interval between the termination trench 12c positioned at an outermost place and the dividing trench 12d is an interval, where the depletion layer is not connected in the discontinuity of the circuit element. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止具有多个沟槽的半导体器件中的击穿电压降低的半导体器件，用于保持形成在周边区域中的击穿电压。解决方案：半导体器件100包括：分为中心区域18A的n型半导体衬底15和围绕中心区域18A的外侧的周边区域18B; 从中心区域18A到周边区域18B形成的p型体区域14; 形成在周边区域18B中的多个终止沟槽12a-12c; 分隔沟槽12d; 和p型扩散区6a-6d形成在围绕每个沟槽的底部的范围内。端子沟槽12a-12c以间隔设置，其中耗尽层以电路元件不连续的方式连接。位于最外侧的终端沟槽12c与划分沟槽12d之间的间隔是间隔，其中耗尽层未连接在电路元件的不连续处。版权所有（C）2010，JPO＆INPIT

28. 发明专利

JP2007173319A Insulated-gate semiconductor device and manufacturing method thereof 有权
标题翻译：绝缘栅半导体器件及其制造方法
公开(公告)号：JP2007173319A
公开(公告)日：2007-07-05
申请号：JP2005365233
申请日：2005-12-19
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKATANI HIDESHI
IPC分类号： H01L29/06 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide an insulated-gate semiconductor device for increasing the breakdown voltage of the main cell region and improving the termination region, and to provide a manufacturing method of the insulated-gate semiconductor device. SOLUTION: The semiconductor device 100 comprises an n + source region 31, a p - body region 41, an n - drift region 12, and an n + drain region 11, successively starting from the upper surface side. A gate trench 21 and a termination trench 62 penetrating the p - body region 41 are also formed. The bottom of each trench is surrounded by p floating regions 51, 53. The gate trench 21 incorporates a gate electrode 22. The innermost trench 621 in the termination trench 62 incorporates a termination gate region 72 electrically connected to the gate electrode 22. The depth of the termination gate region 72 is shallower as compared with the depth (equivalent to the depth of the p - body region 41) of the gate electrode 22 in the gate trench 21. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于增加主单元区域的击穿电压并改善终端区域的绝缘栅极半导体器件，并提供绝缘栅极半导体器件的制造方法。解决方案：半导体器件100包括源极区域31，主体区域41，漂移区域12，，以及从上表面侧开始的n + 漏极区域11。还形成了一个栅极沟槽21和一个穿透该主体区域41的终端沟槽62。每个沟槽的底部由p个浮动区域51,53包围。栅极沟槽21包括栅电极22.终端沟槽62中的最内沟槽621包含电连接到栅极电极22的终端栅极区域72。与栅极沟槽21中的栅电极22的深度（相当于p - 体区域41的深度）相比，端接区域72的深度更浅。 C）2007，JPO＆INPIT

29. 发明专利

JP2007158275A Insulated gate-type semiconductor device and manufacturing method therefor 有权
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：JP2007158275A
公开(公告)日：2007-06-21
申请号：JP2005355419
申请日：2005-12-08
申请人： Toyota Motor Corp , トヨタ自動車株式会社
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , MIYAGI KYOSUKE
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a floating structure, that is, an insulated-gate type semiconductor device that intends further high breakdown voltage, while maintaining ON-resistance characteristics, and to provide a method for manufacturing the same.
SOLUTION: The semiconductor device 100 is produced according to following steps. First, a mask pattern is first formed on the upper surface of a semiconductor substrate, and a gate trench 21 is formed from the upper surface of the semiconductor substrate. Next, ion implantation is performed with a high acceleration voltage. Next, ion implantation is performed at a low acceleration voltage. Next, thermal diffusion treatment is performed. This allows a P-floating region 51, which is to become a longitudinal cross-sectional shape, to be formed in an N
- drift region 12.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有浮动结构的半导体器件，即具有进一步高的击穿电压的绝缘栅型半导体器件，同时保持导通电阻特性，并且提供一种用于制造相同。解决方案：根据以下步骤制造半导体器件100。首先，首先在半导体衬底的上表面上形成掩模图案，并且从半导体衬底的上表面形成栅沟槽21。接下来，以高加速电压进行离子注入。接下来，在低加速电压下进行离子注入。接下来，进行热扩散处理。这样就可以在N＆lt; SP＆gt; - SP漂移区域12中形成一个成为纵向截面形状的P浮动区域。（C）2007，JPO＆INPIT

30. 发明专利

JP2005045123A Trench gate type semiconductor device and its manufacturing device 审中-公开
标题翻译： TRENCH门式半导体器件及其制造设备
公开(公告)号：JP2005045123A
公开(公告)日：2005-02-17
申请号：JP2003279293
申请日：2003-07-24
申请人： Denso Corp , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー
发明人： TAKATANI HIDESHI , HAMADA KIMIMORI , OKURA YASUTSUGU , KUROYANAGI AKIRA
IPC分类号： H01L29/41 , H01L21/336 , H01L29/417 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a trench gate type MOS FET of low ON resistance.
SOLUTION: An n
- -type drift region 2 and a p-channel region 3 are laminated one by one on an n
+ -type substrate 1. An n
+ -type source region 4 and a p
+ -type body region 5 are formed to a stripe in an upper surface of the p-channel region 3. A trench 7 passes through the p(n)-type channel region 3 and attains to the n
- -type drift region 2, and a gate 9 constituted of polycrystalline silicon is buried via a gate insulating film 8. The n
+ -type source region 4 and the p
+ -type body region 5 extend from the p(n)-type channel region 3 to a source electrode 20 and cross the trench 7. The upper surface of the gate 9 is located above the upper surface of the p-channel region 3. A layer insulating film 10 is inside the trench 7, and its upper surface is located below an opening of the trench 7. The source electrode 20, the n
+ -type source region 4 and the p
+ -type body region 5 are electrically connected each in a side wall of the trench 7.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供低导通电阻的沟槽栅型MOS FET。解决方案：将n - / SP>型漂移区2和p沟道区3逐层层叠在n + 型衬底1上.n 在p沟道区域3的上表面中形成有条纹的 + 型源极区域4和ap + 型体区域5.沟槽7通过 p（n）型沟道区3并达到n - SP型漂移区2，并且由多晶硅构成的栅极9通过栅极绝缘膜8埋入。n + 型源极区域4和p + 型体区域5从p（n）型沟道区域3延伸到源电极20并与沟槽7交叉。栅极9的上表面位于p沟道区域3的上表面之上。层间绝缘膜10位于沟槽7内，其上表面位于沟槽7的开口下方。源电极20 ，n + 型源区域4和p + 型体区域5分别电连接在一侧沟槽的墙壁7.版权所有（C）2005，JPO＆NCIPI

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