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21. 发明授权

US06876228B2 Field programmable gate array 有权
标题翻译：现场可编程门阵列
公开(公告)号：US06876228B2
公开(公告)日：2005-04-05
申请号：US10249934
申请日：2003-05-20
申请人： Toshio Sunaga , Hisatada Miyatake , Kohji Kitamura
发明人： Toshio Sunaga , Hisatada Miyatake , Kohji Kitamura
IPC分类号： H01L21/82 , G06F15/78 , H01L21/8246 , H01L27/10 , H01L27/105 , H03K19/173 , H03K19/177
CPC分类号： G06F15/7867
摘要： It is one object of the present invention to provide an FPGA for which the configuration time and the time required for rewriting connection information and logic structure information can be reduced, and for which the size of the area occupied can also be reduced. In order to store connection information for an FPGA, magnetic storage elements MTJ1 to MTJn, which are memory cells of an MRAM, are provided, and using a shift register 71, connection information is written to the magnetic storage elements MTJ1 to MTJn. The shift register 71 includes register elements SR1 to SRn, which correspond to the magnetic storage elements MTJ1 to MTJn, to which the connection information is serially input and stored. When the power is switched on, the connection information stored in the magnetic storage elements MTJ1 to MTJn is latched by latch elements LT1 to LTn, and is output to switching circuits 6 to interconnect logic blocks 51.
摘要翻译：本发明的一个目的是提供一种FPGA，可以减少重写连接信息和逻辑结构信息所需的配置时间和时间，并且还可以减小占用区域的大小。为了存储FPGA的连接信息，提供作为MRAM的存储单元的磁存储元件MTJ1〜MTJn，并且使用移位寄存器71将连接信息写入磁存储元件MTJ1〜MTJn。移位寄存器71包括对应于连续信息串行输入和存储的磁存储元件MTJ1至MTJn的寄存器元件SR1至SRn。当电源接通时，存储在磁存储元件MTJ1至MTJn中的连接信息被锁存元件LT1至LTn锁存，并被输出到开关电路6以互连逻辑块51。

22. 发明申请

US20050042825A1 Image displaying method and image displaying device 失效
标题翻译：图像显示方法和图像显示装置
公开(公告)号：US20050042825A1
公开(公告)日：2005-02-24
申请号：US10494479
申请日：2002-10-29
申请人： Kohji Kitamura , Toshio Sunaga , Hisatada Miyatake
发明人： Kohji Kitamura , Toshio Sunaga , Hisatada Miyatake
IPC分类号： G11C11/15 , G11C11/36 , H01L21/336 , H01L21/84 , H01L27/10 , H01L27/105 , H01L27/146 , H01L27/22
CPC分类号： H01L27/224 , H01L21/84
摘要： Provided is an MRAM memory cell structure capable of preventing generation of parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diode, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrate.
摘要翻译：提供了能够防止寄生晶体管的产生的MRAM存储单元结构。采用二极管作为MRAM存储单元的开关元件。在SOI衬底的表面半导体层上形成共同构成二极管的n型半导体层和p型半导体层。 n型半导体层和p型半导体层沿横向设置并由隔离区隔离，由此二极管与其它元件和衬底电隔离。

23. 发明授权

US5257232A Sensing circuit for semiconductor memory with limited bitline voltage swing 失效
标题翻译：具有有限位线电压摆幅的半导体存储器的感应电路
公开(公告)号：US5257232A
公开(公告)日：1993-10-26
申请号：US847769
申请日：1992-03-05
申请人： Sang H. Dhong , Koji Kitamura , Toshiaki Kirihata , Toshio Sunaga
发明人： Sang H. Dhong , Koji Kitamura , Toshiaki Kirihata , Toshio Sunaga
IPC分类号： G11C11/409 , G11C7/06 , G11C11/407 , G11C11/4091 , G11C13/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： A sensing circuit for dynamic random access memory is disclosed including a pair of bitlines precharged to a first voltage before sensing. A sense amplifier circuit is provided having one node thereof being connected to an external power supply via a switching means including pulsed sense clocks. Control means is provided and is connected to the switching means for controlling the switching means such that the voltage of the power supply is coupled to the node of the sense amplifier for activation for a predetermined period of time, thereby limiting the swing for the high-going bitline to a second voltage lower than said power supply voltage and higher than the first voltage. The reduced bit-line swings are achieved by means of the pulsed sense clocks and the pulse widths for sense clocks are determined by means of a reference bitlines connected to the control means.

24. 发明授权

US08605520B2 Replaceable, precise-tracking reference lines for memory products 有权
标题翻译：存储产品的可更换，精确跟踪参考线
公开(公告)号：US08605520B2
公开(公告)日：2013-12-10
申请号：US12924184
申请日：2010-09-22
申请人： Lejan Pu , Toshio Sunaga
发明人： Lejan Pu , Toshio Sunaga
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C8/14 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2211/5634
摘要： Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts.
摘要翻译：已经实现了提高需要读取诸如MRAM或任何类型的相变存储器（PCM）的参考的半导体存储器阵列的感测操作的可靠性的系统和方法，并且提高了存储器阵列的产量。存储器阵列被分成多个部分，例如部分或部分。参考字线或参考位线或两者部署在多个部分的每一个中。因此，所访问的线路和通信参考线路之间的距离减小，因此寄生参数跟踪能力显着提高。另外备用参考字线或备用参考位线可以部署在多个部分的每一个中。

25. 发明申请

US20070104012A1 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US20070104012A1
公开(公告)日：2007-05-10
申请号：US11555333
申请日：2006-11-01
申请人： Toshio Sunaga
发明人： Toshio Sunaga
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/08 , G11C7/1072 , G11C7/22 , G11C8/12 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： The objective of the present invention is to provide a semiconductor storage device wherein a low active current is obtained by reducing the number of sense amplifiers to be activated at a time. An SDRAM has a divided word line structure, and includes a plurality of banks, each of which includes arrays AR1 to AR64 and 4K main word lines MWL. A row address signal is fetched in response to a row address strobe signal, and a segment address signal is fetched in response to a column address strobe signal. A main row decoder MRD activates main word lines MWL1, MWL5, MWL9 and MWL13 in response to the row address signal, and a segment row decoder SRD selects only an array AR1 in response to a segment address signal, and activates only 1K sense amplifiers SA corresponding to the selected array AR. When the main word lines MWL1, MWL5, MWL9 and MWL13 are activated, the segment word lines in arrays AR2 to AR64 are not activated, so that data are not destroyed.
摘要翻译：本发明的目的是提供一种半导体存储装置，其中通过减少一次要激活的读出放大器的数量来获得低有功电流。 SDRAM具有划分的字线结构，并且包括多个存储体，每个存储体包括阵列AR 1至AR 64和4K主字线MWL。响应于行地址选通信号取出行地址信号，响应于列地址选通信号取出段地址信号。主行解码器MRD响应于行地址信号激活主字线MWL 1，MWL 5，MWL 9和MWL 13，并且段行解码器SRD响应于段地址信号仅选择阵列AR 1，并且激活只有1K个读出放大器SA对应于所选阵列AR。当主字线MWL 1，MWL 5，MWL 9和MWL 13被激活时，阵列AR 2至AR 64中的段字线不被激活，使得数据不被破坏。

26. 发明授权

US06977857B2 DRAM and refresh method thereof 失效
标题翻译： DRAM及其刷新方法
公开(公告)号：US06977857B2
公开(公告)日：2005-12-20
申请号：US10446400
申请日：2003-05-28
申请人： Masaya Mori , Toshio Sunaga , Shinpei Watanabe
发明人： Masaya Mori , Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4067
摘要： The present invention relates to a DRAM having a memory array that is divided into a plurality of memory blocks. A memory block having a long data retention time is selected from the plurality of memory blocks and a logical address is allocated to the selected memory block. The selected memory block is refreshed at longer time intervals compared to conventional DRAMs resulting in lower power consumption.
摘要翻译：本发明涉及具有被划分成多个存储块的存储器阵列的DRAM。从多个存储块中选择具有长数据保持时间的存储块，并且将逻辑地址分配给所选存储块。与常规DRAM相比，所选择的存储器块以更长的时间间隔被刷新，导致较低的功耗。

27. 发明授权

US06650573B2 Data input/output method 失效
公开(公告)号：US06650573B2
公开(公告)日：2003-11-18
申请号：US10063059
申请日：2002-03-15
申请人： Toshio Sunaga , Shinpei Watanabe
发明人： Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： The present invention discloses a method for data input/output for memory which minimizes losses of data interruption when switching between reading and writing. A method for data input/output comprises the steps of: holding predetermined data from memory array 12 upon m-th (m is integer) read command; outputting the predetermined data to common I/O 30 and holding new data from memory array 12 upon (m+1)-th read command; holding predetermined data from common I/O 30 upon n-th (n is integer) write command; and storing the predetermined data in memory array 12 and holding new data from common I/O 30 upon (n+1)-th write command.

28. 发明授权

US08488357B2 Reference cell architectures for small memory array block activation 有权
标题翻译：小型存储器阵列块激活的参考单元结构
公开(公告)号：US08488357B2
公开(公告)日：2013-07-16
申请号：US12925492
申请日：2010-10-22
申请人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
发明人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
IPC分类号： G11C5/08
CPC分类号： G11C5/063 , G11C7/14 , G11C8/12 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675
摘要： Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.
摘要翻译：已经实现了用于实现参考电流以提高分段半导体存储器阵列的感测操作的可靠性的系统和方法。本发明的优选实施例包括MRAM阵列，但是本发明可以应用于需要在小的分段阵列上访问的任何其他存储器。本发明的所有实施例包括在相邻位线中或在段到段折叠的位线中的折叠位线方案。在两个实施例中，通过读取字线和写入选择线的金属层实现了每个第二段中的多晶硅字线的交替捆扎。一个实施例在要读取的所选择的段的两侧上存储了1个和0个单元。

29. 发明申请

US20120099358A1 Reference cell architectures for small memory array block activation 有权
标题翻译：小型存储器阵列块激活的参考单元结构
公开(公告)号：US20120099358A1
公开(公告)日：2012-04-26
申请号：US12925492
申请日：2010-10-22
申请人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
发明人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
IPC分类号： G11C5/08 , G11C5/06
CPC分类号： G11C5/063 , G11C7/14 , G11C8/12 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675
摘要： Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.
摘要翻译：已经实现了用于实现参考电流以提高分段半导体存储器阵列的感测操作的可靠性的系统和方法。本发明的优选实施例包括MRAM阵列，但是本发明可以应用于需要在小的分段阵列上访问的任何其他存储器。本发明的所有实施例包括在相邻位线中或在段到段折叠的位线中的折叠位线方案。在两个实施例中，通过读取字线和写入选择线的金属层实现了每个第二段中的多晶硅字线的交替捆扎。一个实施例在要读取的所选择的段的两侧上存储了1个和0个单元。

30. 发明授权

US07469243B2 Method and device for searching fixed length data 失效
标题翻译：用于搜索固定长度数据的方法和设备
公开(公告)号：US07469243B2
公开(公告)日：2008-12-23
申请号：US10707943
申请日：2004-01-27
申请人： Masaya Mori , Shinpei Watanabe , Yoshihisa Takatsu , Toshio Sunaga
发明人： Masaya Mori , Shinpei Watanabe , Yoshihisa Takatsu , Toshio Sunaga
IPC分类号： G06F7/00 , G06F12/00 , G06F15/16
CPC分类号： G06F17/30949 , G06F7/02 , Y10S707/99933
摘要： Embodiments of the present invention provide method and device for searching fixed length data. The device includes a hash operation means for operating and outputting a hash value of inputted fixed length data, a data table memory consisting of N numbers of memory banks, where N is an integer that is more than and equal to 2, the data table memory for storing a data table holding a large number of fixed length data, a pointer table memory for storing a memory pointer table holding a memory address at which each fixed length datum is stored with the hash value as an index, and a comparison means for simultaneously comparing a plurality of fixed length data stored at the same memory address in the N numbers of memory banks with a single fixed length datum inputted to the hash operation means, the comparison means for outputting results of the comparison.
摘要翻译：本发明的实施例提供了用于搜索固定长度数据的方法和装置。该装置包括用于操作和输出输入的固定长度数据的散列值的散列操作装置，由N个存储体组成的数据表存储器，其中N是大于等于2的整数，数据表存储器用于存储保持大量固定长度数据的数据表;指针表存储器，用于存储存储指针表，该存储器指针表保存以散列值作为索引存储每个固定长度数据的存储器地址;以及比较装置，用于同时将存储在N个存储体组中的相同存储器地址的多个固定长度数据与输入到散列运算装置的单个固定长度数据进行比较，该比较装置用于输出比较结果。

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