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21. 发明申请

US20090259830A1 Quantifying Completion Stalls Using Instruction Sampling 失效
标题翻译：使用指令采样量化完成失速
公开(公告)号：US20090259830A1
公开(公告)日：2009-10-15
申请号：US12099944
申请日：2008-04-09
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/3802 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F9/3885 , G06F11/3466 , G06F11/348 , G06F2201/86
摘要： A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are.
摘要翻译：公开了一种用于在具有分支预测的无序超标量处理器中收集关于完成停顿的度量的方法，计算机程序产品和数据处理系统。本发明的优选实施例有选择地对特定指令（或指令类别）进行采样。每个选定的指令在通过处理器数据路径时被标记（标记），用于由性能监视单元监视。标记指令的进度由性能监控单元进行监控，各种失速计数器由标记指令和指令组的进度触发。停顿计数器计数周期，以指示何时发生与特定指令相关的某些延迟以及延迟的严重程度。

22. 发明申请

US20090024878A1 Apparatus and Computer Program Product in a Processor for Performing In-Memory Tracing Using Existing Communication Paths 失效
标题翻译：用于使用现有通信路径执行内存中跟踪的处理器中的设备和计算机程序产品
公开(公告)号：US20090024878A1
公开(公告)日：2009-01-22
申请号：US12201557
申请日：2008-08-29
申请人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
发明人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/2268 , G06F11/348
摘要： An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.
摘要翻译：公开了一种用于使用现有系统总线在处理器中执行存储器内硬件跟踪的装置和计算机程序产品。处理器包括利用系统总线耦合在一起的多个处理单元。处理单元包括控制系统存储器的存储器控制器。利用系统总线在处理单元之间传送信息。信息根据标准系统总线协议进行格式化。使用直接耦合到系统总线的硬件跟踪功能来捕获硬件跟踪数据。系统总线用于将硬件跟踪数据发送到存储器控制器以存储在系统存储器中。存储器控制器直接耦合到系统总线。硬件跟踪数据根据标准系统总线协议进行格式化，以便通过系统总线进行传输。

23. 发明申请

US20090006825A1 Method, Apparatus, and Computer Program Product in a Processor for Concurrently Sharing a Memory Controller Among a Tracing Process and Non-Tracing Processes Using a Programmable Variable Number of Shared Memory Write Buffers 失效
标题翻译：处理器中的方法，装置和计算机程序产品，用于在使用可编程可变数量的共享存储器写缓冲器的跟踪处理和非跟踪过程中并发共享存储器控制器
公开(公告)号：US20090006825A1
公开(公告)日：2009-01-01
申请号：US12210005
申请日：2008-09-12
申请人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
发明人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
IPC分类号： G06F9/30
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
摘要翻译：公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。硬件跟踪设备捕获处理器中的硬件跟踪数据。硬件跟踪工具包含在处理器内。使用系统总线将硬件跟踪数据传输到系统存储器。系统内存包含在系统中。当硬件跟踪数据被传送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。系统内存的一部分用于存储跟踪数据。系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。

24. 发明授权

US07194608B2 Method, apparatus and computer program product for identifying sources of performance events 失效
标题翻译：用于识别性能事件来源的方法，设备和计算机程序产品
公开(公告)号：US07194608B2
公开(公告)日：2007-03-20
申请号：US11405050
申请日：2006-04-17
申请人： Alexander Erik Mericas
发明人： Alexander Erik Mericas
IPC分类号： G06F11/30
CPC分类号： G06F9/3885 , G06F9/3017 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3861 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： Event vectors are included in an instruction tracking structure of a processor to collect history for every instruction flowing through the processor. Such an event vector, by its nature, cannot be whole until the vector's corresponding instruction completes. However, some information for the event vector is collected earlier, i.e., as the instruction flows through the processor prior to completion. Upon completion of the instruction, the instruction's event vector is examined. In each case a determination is made from the instruction history contained in the event vector as to whether a particular instruction has or has not caused or encountered an event of interest. Responsive to the determination, and possibly other information, a selection is made between saving event vector information and discarding the information.
摘要翻译：事件向量包括在处理器的指令跟踪结构中，以收集流过处理器的每个指令的历史。这样一个事件向量，其性质，直到向量的相应指令完成才能完成。然而，先前收集事件向量的一些信息，即当指令在完成之前流经处理器时。指令完成后，检查指令的事件向量。在每种情况下，从包含在事件向量中的指令历史确定特定指令是否具有或没有引起或遇到感兴趣的事件。响应于确定以及可能的其他信息，在保存事件向量信息和丢弃信息之间进行选择。

25. 发明授权

US06748522B1 Performance monitoring based on instruction sampling in a microprocessor 失效
标题翻译：基于微处理器中指令采样的性能监控
公开(公告)号：US06748522B1
公开(公告)日：2004-06-08
申请号：US09703346
申请日：2000-10-31
申请人： Dennis Gerard Gregoire , Alexander Erik Mericas , Joel M. Tendler
发明人： Dennis Gerard Gregoire , Alexander Erik Mericas , Joel M. Tendler
IPC分类号： G06F1130
CPC分类号： G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： The problem identified above is addressed in large part by a microprocessor as disclosed herein. The microprocessor includes a dispatch unit configured to receive a set of instructions from an instruction cache and to forward the set of instructions to an issue queue when the instructions are ready for execution. The dispatch unit may include sampling logic that is configured to select one of the instructions for performance monitoring from the set of instructions. The microprocessor further includes a performance monitor unit enabled to monitor performance characteristics of the selected instruction as it executes. The sampling logic may identify the instruction selected for monitoring as the instruction occupying an eligible position within the set of instructions. The eligible position from which the monitored instruction is selected may vary with each subsequent set of instructions. The sampling logic may include a selection mask that contains an asserted bit that identifies the position within the set of instructions from which the selected instruction is chosen. The selection mask may include a single bit for each position in the set of instructions and may be implemented as a shift register that periodically rotates the eligible position. The rotation of the eligible bit position may occur every clock cycle, every dispatch cycle, or at some another suitable synchronous or asynchronous interval. The selection mask may contain multiple asserted bits and may include a filter circuit that generates a selection vector based on the selection mask where the selection vector includes only a single asserted bit.
摘要翻译：上述问题在很大程度上由本文公开的微处理器来解决。微处理器包括配置单元，配置为从指令高速缓存接收一组指令，并且当指令准备好执行时将指令集转发到发行队列。调度单元可以包括采样逻辑，其被配置为从该组指令中选择用于性能监视的指令之一。微处理器还包括一个性能监视器单元，能够在执行时监视所选指令的性能特征。采样逻辑可以将所选择的用于监视的指令识别为在该组指令内占据合格位置的指令。所选择的被监视指令的合格位置可随随后的指令集而变化。采样逻辑可以包括选择掩码，其包含标识位于所选择的指令所选择的指令集内的位置的有效位。选择掩模可以包括指令集中的每个位置的单个位，并且可以被实现为周期性地旋转合格位置的移位寄存器。合格位位置的旋转可以在每个时钟周期，每个调度周期或在另一个合适的同步或异步间隔中发生。选择掩码可以包含多个被断言的位，并且可以包括滤波器电路，该滤波器电路基于选择矢量生成选择向量，其中选择向量仅包括单个被断言位。

26. 发明授权

US06629170B1 Method and apparatus for a byte lane selectable performance monitor bus 失效
标题翻译：用于字节通道可选性能监视总线的方法和装置
公开(公告)号：US06629170B1
公开(公告)日：2003-09-30
申请号：US09436110
申请日：1999-11-08
申请人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
发明人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
IPC分类号： G06F1300
CPC分类号： G06F11/348 , G06F11/349 , G06F2201/88
摘要： A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.
摘要翻译：多级字节通道可选择总线。在优选实施例中，性能监视模式中的总线包括多个字节通道和选择机构。选择机制从多个信号中获取希望被监视的那些信号的子集，并将该子集信号放置在输入到PMU的字节通道上。可能被监视的多个信号的数量大于字节通道的数量，并且也大于PMU计数器的数量。

27. 发明授权

US06550002B1 Method and system for detecting a flush of an instruction without a flush indicator 失效
标题翻译：用于检测没有冲洗指示器的指令冲洗的方法和系统
公开(公告)号：US06550002B1
公开(公告)日：2003-04-15
申请号：US09435067
申请日：1999-11-04
申请人： Joel Roger Davidson , Hung Oui Le , Alexander Erik Mericas
发明人： Joel Roger Davidson , Hung Oui Le , Alexander Erik Mericas
IPC分类号： G06F1130
CPC分类号： G06F9/3836 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F11/3466
摘要： A method and system for detecting flushed instructions without a flush indicator is provided. In order to monitor the flushing of an instruction in an instruction pipeline of a processor, an instruction is selected as a sampled instruction and the progress of the sampled instruction through the instruction pipeline is monitored. Upon selection of an instruction as a sampled instruction, a countdown value is initialized to a value equal to the maximum number of instructions within the instruction pipeline, and as instructions complete, the countdown value is decremented. If progress of the sampled instruction is detected as the instruction moves through the instruction pipeline, the countdown value is reinitialized. If the countdown value reaches zero, then a flush of the sampled instruction from the instruction pipeline is presumed, and an indication that the sampled instruction has been flushed is generated. In response to the indication that the sampled instruction has been flushed, a subsequent instruction may be selected as a subsequently sampled instruction.
摘要翻译：提供一种用于检测没有冲洗指示器的冲洗指令的方法和系统。为了监视处理器的指令流水线中的指令的刷新，选择指令作为采样指令，并监视通过指令流水线的采样指令的进度。在选择指令作为采样指令时，将倒数值初始化为等于指令流水线内最大指令数的值，并且随着指令的完成，递减计数值。如果指令在指令流水线中移动，则检测到采样指令的进度，则重新初始化倒数值。如果倒计时值为零，则假定来自指令流水线的采样指令的刷新，并且产生已经刷新了采样指令的指示。响应于采样指令已被刷新的指示，随后的指令可以被选择为随后采样的指令。

28. 发明授权

US06446029B1 Method and system for providing temporal threshold support during performance monitoring of a pipelined processor 有权
标题翻译：用于在流水线处理器的性能监视期间提供临时阈值支持的方法和系统
公开(公告)号：US06446029B1
公开(公告)日：2002-09-03
申请号：US09343449
申请日：1999-06-30
申请人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick
发明人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick
IPC分类号： G06F1500
CPC分类号： G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and system for monitoring the performance of a instruction pipeline is provided. The processor may contain a performance monitor for monitoring for the occurrence of an event within a data processing system. An event to be monitored may be specified through software control, and the occurrence of the specified event is monitored during the execution of an instruction in the execution pipeline of the processor. A particular instruction may be specified to execute within a threshold time for each stage of the instruction pipeline. The specified event may be the completion of a single tagged instruction beyond the specified threshold interval for a stage of the instruction pipeline. The performance monitor may contain a number of counters for counting multiple occurrences of specified events during the execution of multiple instructions, in which case the specified events may be the completion of tagged instructions beyond a threshold interval for any stage of the multiple stages of the execution pipeline. As the instruction moves through the processor, the performance monitor collects the events and provides the events for optimization analysis.
摘要翻译：提供了一种用于监视指令流水线性能的方法和系统。处理器可以包含用于监视数据处理系统内的事件发生的性能监视器。可以通过软件控制指定要监视的事件，并且在执行处理器的执行流水线中的指令期间监视指定事件的发生。可以指定特定指令以在指令流水线的每个阶段的阈值时间内执行。指定的事件可以是超出指令流水线阶段的指定阈值间隔的单个标记指令的完成。性能监视器可以包含多个计数器，用于在执行多个指令期间对多次发生的指定事件进行计数，在这种情况下，指定事件可以是执行多个执行阶段的任何阶段的阈值间隔之外的已标记指令的完成管道。当指令移动通过处理器时，性能监视器收集事件并提供事件进行优化分析。

29. 发明授权

US10169187B2 Processor core having a saturating event counter for making performance measurements 有权
公开(公告)号：US10169187B2
公开(公告)日：2019-01-01
申请号：US12858497
申请日：2010-08-18
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F11/34
摘要： A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.

30. 发明申请

US20120046912A1 PROCESSOR CORE HAVING A SATURATING EVENT COUNTER FOR MAKING PERFORMANCE MEASUREMENTS 审中-公开
标题翻译：具有制作性能测量的饱和活动计数器的处理器芯
公开(公告)号：US20120046912A1
公开(公告)日：2012-02-23
申请号：US12858497
申请日：2010-08-18
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F15/00
CPC分类号： G06F11/348 , G06F2201/88
摘要： A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.
摘要翻译：包括饱和计数器的性能监视器提供事件频率的相对度量，而不需要最小轮询速率或周期性复位来避免或考虑计数器溢出。饱和计数器在检测到事件时增加，并且如果在预定时间段内未检测到事件，则递减计数器。检测周期可以是可编程的，并且可以通过实时时钟，处理器或指令周期来确定。可以选择多个事件类型用于检测和输入到单个计数器，或者可以为各种事件类型提供多个事件计数器。饱和计数器可以另外在所选择的操作模式中周期性地复位，并结合在计数器上执行的递减动作。

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