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1. 发明授权

US06748522B1 Performance monitoring based on instruction sampling in a microprocessor 失效
标题翻译：基于微处理器中指令采样的性能监控
公开(公告)号：US06748522B1
公开(公告)日：2004-06-08
申请号：US09703346
申请日：2000-10-31
申请人： Dennis Gerard Gregoire , Alexander Erik Mericas , Joel M. Tendler
发明人： Dennis Gerard Gregoire , Alexander Erik Mericas , Joel M. Tendler
IPC分类号： G06F1130
CPC分类号： G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： The problem identified above is addressed in large part by a microprocessor as disclosed herein. The microprocessor includes a dispatch unit configured to receive a set of instructions from an instruction cache and to forward the set of instructions to an issue queue when the instructions are ready for execution. The dispatch unit may include sampling logic that is configured to select one of the instructions for performance monitoring from the set of instructions. The microprocessor further includes a performance monitor unit enabled to monitor performance characteristics of the selected instruction as it executes. The sampling logic may identify the instruction selected for monitoring as the instruction occupying an eligible position within the set of instructions. The eligible position from which the monitored instruction is selected may vary with each subsequent set of instructions. The sampling logic may include a selection mask that contains an asserted bit that identifies the position within the set of instructions from which the selected instruction is chosen. The selection mask may include a single bit for each position in the set of instructions and may be implemented as a shift register that periodically rotates the eligible position. The rotation of the eligible bit position may occur every clock cycle, every dispatch cycle, or at some another suitable synchronous or asynchronous interval. The selection mask may contain multiple asserted bits and may include a filter circuit that generates a selection vector based on the selection mask where the selection vector includes only a single asserted bit.
摘要翻译：上述问题在很大程度上由本文公开的微处理器来解决。微处理器包括配置单元，配置为从指令高速缓存接收一组指令，并且当指令准备好执行时将指令集转发到发行队列。调度单元可以包括采样逻辑，其被配置为从该组指令中选择用于性能监视的指令之一。微处理器还包括一个性能监视器单元，能够在执行时监视所选指令的性能特征。采样逻辑可以将所选择的用于监视的指令识别为在该组指令内占据合格位置的指令。所选择的被监视指令的合格位置可随随后的指令集而变化。采样逻辑可以包括选择掩码，其包含标识位于所选择的指令所选择的指令集内的位置的有效位。选择掩模可以包括指令集中的每个位置的单个位，并且可以被实现为周期性地旋转合格位置的移位寄存器。合格位位置的旋转可以在每个时钟周期，每个调度周期或在另一个合适的同步或异步间隔中发生。选择掩码可以包含多个被断言的位，并且可以包括滤波器电路，该滤波器电路基于选择矢量生成选择向量，其中选择向量仅包括单个被断言位。

2. 发明授权

US06694427B1 Method system and apparatus for instruction tracing with out of order processors 失效
标题翻译：用于无序处理器的指令跟踪的方法系统和装置
公开(公告)号：US06694427B1
公开(公告)日：2004-02-17
申请号：US09552859
申请日：2000-04-20
申请人： Alexander Erik Mericas , William John Starke , Joel M. Tendler
发明人： Alexander Erik Mericas , William John Starke , Joel M. Tendler
IPC分类号： G06F900
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/3808 , G06F9/3842 , G06F11/3636
摘要： A method, system and apparatus for instruction tracing with out of order speculative processors. With the present invention, information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions fetched by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during fetching of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions fetched is known from the fetched instructions information stored in the trace storage device. Hence the instruction stream may be reconstructed from the information stored in the trace storage device.
摘要翻译：用于无序推测处理器的指令跟踪的方法，系统和装置。利用本发明，与指令高速缓存和数据高速缓存的状态相对应的信息与对应于由处理器获取的指令的信息一起存储在跟踪存储设备中。当需要缓存加载时，更新的缓存信息被存储在跟踪存储设备中。因此，可以从存储在跟踪存储装置中的信息中知道在取指令期间的任何时候的高速缓存的状态。此外，从存储在跟踪存储设备中的获取的指令信息中可以获得所提取的特定指令。因此，可以从存储在跟踪存储设备中的信息重建指令流。

3. 发明授权

US06415378B1 Method and system for tracking the progress of an instruction in an out-of-order processor 失效
标题翻译：用于跟踪无序处理器中的指令进度的方法和系统
公开(公告)号：US06415378B1
公开(公告)日：2002-07-02
申请号：US09343359
申请日：1999-06-30
申请人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick , Joel M. Tendler
发明人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick , Joel M. Tendler
IPC分类号： G06F1100
CPC分类号： G06F11/3466
摘要： A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.
摘要翻译：提供了一种用于调试指令管线内的指令执行的方法和系统。数据处理系统中的处理器包含指令流水线单元。指令可以被标记，并且响应于指令流水线单元完成其对带标签的指令的处理，声明级完成信号。流水线处理器外部的执行监视器在执行标记指令期间监视阶段完成信号。执行监视器可以是在执行监视器的显示装置上实时显示级完成信号的逻辑分析器。可以基于诸如指令的地址的指令选择规则来选择要被标记的指令。

4. 发明授权

US06539500B1 System and method for tracing 失效
标题翻译：系统和追踪方法
公开(公告)号：US06539500B1
公开(公告)日：2003-03-25
申请号：US09428410
申请日：1999-10-28
申请人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
发明人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
IPC分类号： G06F1100
CPC分类号： G06F11/3636
摘要： The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed. Also since the trace function is part of the multiprocessor architecture its speed of operation will scale with the speed of the processors without modification.
摘要翻译：本发明公开了一种用于在计算机系统中实现指令跟踪的系统和方法，特别是具有紧耦合的共享处理器中央处理器单元（CPU）的计算机系统。每个处理器通常是通过设计修改的目的处理器，以允许指令执行并同时被存储并转发到可用作跟踪缓冲器的共享存储器。由于每个处理器是通用目的，因此可以通过其中一个可以在任一处理器上编写和执行的程序之一进行跟踪所需的跟踪例程。其中一个处理器可以运行，收集和分析其他处理器的执行和存储指令。由于处理器可以在单个芯片上，写入和读取执行的指令的共享存储器总线可以高速运行。此外，由于跟踪功能是多处理器架构的一部分，因此操作速度将随着处理器的速度而不变化。

5. 发明申请

US20140059334A1 Autonomic Hotspot Profiling Using Paired Performance Sampling 有权
标题翻译：使用配对性能采样的自动热点分析
公开(公告)号：US20140059334A1
公开(公告)日：2014-02-27
申请号：US14067212
申请日：2013-10-30
申请人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
发明人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F8/443 , G06F8/4442 , G06F9/3861 , G06F11/34 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.
摘要翻译：处理器性能分析器能够用于识别由微处理器通过随机采样来执行的程序中导致性能问题的特定指令，以找到诸如高速缓存未命中或分支误预测的特定事件类型的最坏情况的违规者。跟踪导致特定事件的所有指令会生成大量数据日志，创建性能损失，并使代码分析更加困难。然而，通过识别和跟踪随机事件样本中的最坏罪犯，而不必对所有事件进行散列，从而导致性能分析器的较小内存需求，降低性能影响，同时分析并降低分析程序以识别主要性能问题的复杂性，这反过来，可以在较短的开发人员时间内更好地优化程序。

6. 发明授权

US08612730B2 Hardware assist thread for dynamic performance profiling 失效
标题翻译：用于动态性能分析的硬件辅助线
公开(公告)号：US08612730B2
公开(公告)日：2013-12-17
申请号：US12796124
申请日：2010-06-08
申请人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
发明人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/327 , G06F11/3466 , G06F2201/865 , G06F2201/88
摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.
摘要翻译：一种用于管理程序中的指令的运行的方法和数据处理系统。数据处理系统的处理器接收监视单元的监视指令。处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。处理器将程序中指令的运行情况从主线程更改为辅助线程。

7. 发明申请

US20120124560A1 Autonomic Hotspot Profiling Using Paired Performance Sampling 失效
标题翻译：使用配对性能采样的自动热点分析
公开(公告)号：US20120124560A1
公开(公告)日：2012-05-17
申请号：US12946959
申请日：2010-11-16
申请人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
发明人： Venkat Rajeev Indukuru , Daniel Owen , Alexander Erik Mericas , John Fred Spannaus
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F8/443 , G06F8/4442 , G06F9/3861 , G06F11/34 , G06F11/3471 , G06F11/3476 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.
摘要翻译：处理器性能分析器能够用于识别由微处理器通过随机采样来执行的程序中导致性能问题的特定指令，以找到诸如高速缓存未命中或分支误预测的特定事件类型的最坏情况的违规者。跟踪导致特定事件的所有指令会生成大量数据日志，创建性能损失，并使代码分析更加困难。然而，通过识别和跟踪随机事件样本中的最坏罪犯，而不必对所有事件进行散列，从而导致性能分析器的较小内存需求，降低性能影响，同时分析并降低分析程序以识别主要性能问题的复杂性，这反过来，可以在较短的开发人员时间内更好地优化程序。

8. 发明授权

US08055809B2 System and method for distributing signal with efficiency over microprocessor 失效
标题翻译：通过微处理器分配信号的系统和方法
公开(公告)号：US08055809B2
公开(公告)日：2011-11-08
申请号：US12343594
申请日：2008-12-24
申请人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger , Daniel Becker
发明人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger , Daniel Becker
IPC分类号： G06F3/00
CPC分类号： G06F13/4247 , G06F11/3466 , G06F11/348 , G06F11/349 , G06F2201/88
摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.
摘要翻译：一种用于通过微处理器分配信号的系统和相关方法。性能监视单元（PMU）将配置信号发送到单元以监视本机发生的事件。该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。配置总线将配置信号从PMU发送到单元以设置单元以报告事件。该单元通过事件总线向PMU发送事件信号。该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。

9. 发明授权

US07913123B2 Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers 失效
标题翻译：在跟踪过程和使用可编程可变数量的共享内存写入缓冲区的非跟踪过程之间同时共享内存控制器
公开(公告)号：US07913123B2
公开(公告)日：2011-03-22
申请号：US12210005
申请日：2008-09-12
申请人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
发明人： Ra'ed Mohammad Al-Omari , Alexander Erik Mericas , William John Starke
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
摘要翻译：公开了一种装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。硬件跟踪设备捕获处理器中的硬件跟踪数据。硬件跟踪工具包含在处理器内。使用系统总线将硬件跟踪数据传输到系统存储器。系统内存包含在系统中。当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。系统内存的一部分用于存储跟踪数据。系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。

10. 发明授权

US06970999B2 Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters 失效
标题翻译：使用多个分配的计数器计数指令表的等待时间，刷新，补充和指令执行
公开(公告)号：US06970999B2
公开(公告)日：2005-11-29
申请号：US10210415
申请日：2002-07-31
申请人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
发明人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
IPC分类号： G06F9/38 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855
摘要： A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.
摘要翻译：一种用于分析处理器中每条指令（CPI）性能的循环的方法和系统。完成表对应于要由处理器处理的组中的指令。一个空的完成表表明有一些类型的灾难导致表冲洗。当表为空时，位于处理器中的性能监视单元（PMU）中的性能监视计数器（PMC）会计数表为空的时钟周期数。优选地，根据完成表为空的原因，使用单独的PMC。第二个PMC同样计算重新填充空完成表的时钟周期数。第三个PMC计算在完成表中实际执行指令花费的时钟周期数。 PMC中的信息可用于评估CPI性能下降的真正原因。

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