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21. 发明专利

JP2011009695A Nonvolatile semiconductor memory device and depletion type mos transistor 审中-公开
标题翻译：非易失性半导体存储器件和漏电型MOS晶体管
公开(公告)号：JP2011009695A
公开(公告)日：2011-01-13
申请号：JP2010029218
申请日：2010-02-12
申请人： Toshiba Corp , 株式会社東芝
发明人： KUTSUKAKE HIROYUKI , GOMIKAWA KENJI , KATO TOKO , NOGUCHI MITSUHIRO , ENDO MASATO
IPC分类号： H01L27/115 , H01L21/768 , H01L21/8247 , H01L27/10 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/088 , H01L21/823418 , H01L27/11526 , H01L27/11529 , H01L29/0847 , H01L29/41775 , H01L29/7838
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and a depletion type MOS transistor, which improve a breakdown voltage of a transistor and improve operation reliability.SOLUTION: The transistor is equipped with: a gate electrode 26; a channel region 22 having a first impurity concentration; a source and drain diffusion region 21 having a second impurity concentration higher than the first impurity concentration; an overlapping region 24 which is formed in a region where the channel region 22 overlaps the source and drain diffusion region 21 and has a third impurity concentration higher than the second impurity concentration region; a contact region 23 having a fourth impurity concentration higher than the second impurity concentration; and an impurity diffusion region 27 which is formed inside a part of the source and drain diffusion region 21 and has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region 27 is in contact with the contact region 23 and away from the overlapping region 24.
摘要翻译：要解决的问题：提供一种提高晶体管的击穿电压并提高操作可靠性的非易失性半导体存储器件和耗尽型MOS晶体管。解决方案：晶体管配备有：栅电极26; 具有第一杂质浓度的沟道区22; 具有比第一杂质浓度高的第二杂质浓度的源极和漏极扩散区21; 形成在沟道区域22与源极和漏极扩散区域21重叠并且具有高于第二杂质浓度区域的第三杂质浓度的区域中的重叠区域24; 具有高于第二杂质浓度的第四杂质浓度的接触区23; 以及杂质扩散区域27，其形成在源极和漏极扩散区域21的一部分内，并且具有高于第二杂质浓度且低于第四杂质浓度的第五杂质浓度。杂质扩散区域27与接触区域23接触并远离重叠区域24。

22. 发明专利

JP2010251477A Semiconductor memory device and manufacturing method of the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2010251477A
公开(公告)日：2010-11-04
申请号：JP2009098302
申请日：2009-04-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , NOGUCHI MITSUHIRO , NAKAJIMA HIROOMI , ENDO MASATO
IPC分类号： H01L27/10
CPC分类号： H01L27/105 , H01L27/1021 , H01L27/1052 , H01L27/24
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that is advantageous to the increase of power consumption and a method of manufacturing the same.
SOLUTION: Each semiconductor memory device has a plurality of three-dimensionally structured memory cell arrays 10 that each have two or more memory cells and are multi-laminated on the semiconductor substrate 35, a first conductivity-type first well 43 prepared in a semiconductor substrate 35, and an element isolation insulating film STI having its bottom face at a position shallower than that of the first well 43 in the first well 43 and embedded and arranged in the semiconductor substrate 35. Further, it has a second well 44 having its bottom face at a position shallower than that of the first well 43 in the first well 43 (DP
摘要翻译：解决的问题：提供有利于增加功耗的半导体存储器件及其制造方法。解决方案：每个半导体存储器件具有多个三维结构的存储单元阵列10，每个存储单元阵列具有两个或更多个存储单元，并且多层叠在半导体衬底35上，第一导电型第一阱43 半导体衬底35和元件隔离绝缘膜STI，其底面位于比第一阱43中的第一阱43浅的位置，并嵌入并布置在半导体衬底35中。此外，它具有第二阱44 其底面位于比元件隔离绝缘膜STI的至少部分底面旁边准备的第一孔43（DP

23. 发明专利

JP2010123186A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2010123186A
公开(公告)日：2010-06-03
申请号：JP2008295846
申请日：2008-11-19
申请人： Toshiba Corp , 株式会社東芝
发明人： KUTSUKAKE HIROYUKI , GOMIKAWA KENJI , NOGUCHI MITSUHIRO , SUGIMAE KIKUKO , ENDO MASATO , FUTAYAMA TAKUYA , KATO KOJI , UCHIDA KANAE
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11521 , H01L27/11526
摘要： PROBLEM TO BE SOLVED: To improve reliability of a high breakdown voltage type transistor which transfers a high potential to word lines. SOLUTION: The nonvolatile semiconductor memory includes N-channel MOS transistors 21(BK1) to be connected between the word lines WL1-WLn in a NAND block BK1 and potential transfer lines CG1-CGn, and N-channel MOS transistors 21(BK2) to be connected between the word lines WL1-WLn in a NAND block BK2 and the potential transfer lines CG1-CGn. When data are erased with respect to a memory cell MC in the NAND block BK1, a first potential (Vera+Vadd) with a plus value is applied to a semiconductor substrate, and a second potential Vadd with a plus value lower than the first potential (Vera+Vadd) is applied to the potential transfer lines CG1-CGn, to turn the N-channel MOS transistors 21(BK1) on and to turn the N-channel MOS transistors 21(BK2) off. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提高将高电位转移到字线的高耐压型晶体管的可靠性。解决方案：非易失性半导体存储器包括要连接在NAND块BK1中的字线WL1-WLn和电位传输线CG1-CGn之间的N沟道MOS晶体管21（BK1）和N沟道MOS晶体管21（ BK2）连接在NAND块BK2中的字线WL1-WLn和电位传输线CG1-CGn之间。当相对于NAND块BK1中的存储单元MC擦除数据时，具有正值的第一电位（Vera + Vadd）被施加到半导体衬底，并且具有低于第一电位的正值的第二电位Vadd （Vera + Vadd）施加到电位传输线CG1-CGn，使N沟道MOS晶体管21（BK1）导通并使N沟道MOS晶体管21（BK2）截止。版权所有（C）2010，JPO＆INPIT

24. 发明专利

JP2009054942A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2009054942A
公开(公告)日：2009-03-12
申请号：JP2007222601
申请日：2007-08-29
申请人： Toshiba Corp , 株式会社東芝
发明人： GOMIKAWA KENJI , WATANABE SHOICHI , NOGUCHI MITSUHIRO , IGUCHI SUNAO
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To prevent the degradation in the performance of a peripheral transistor even when using a high-k material for an inter-electrode dielectric.
SOLUTION: A memory cell is provided with a floating gate electrode 8 formed on a first channel region between first and second diffusion layers through a first gate insulating film 7, and control gate electrodes 2 and 11 formed on the floating gate electrode 8 through a first inter-electrode dielectric 10. The peripheral transistor is provided with a lower electrode 17 formed on a second channel region between third and fourth diffusion layer through second gate insulating films 16A and 16B, and upper electrodes 3 and 19 formed on the lower electrode 17 through a second inter-electrode dielectric 18. The lower electrode 17 and the upper electrodes 3 and 19 are electrically connected together through an opening provided on the second inter-electrode dielectric 18. The first and second inter-electrode dielectrics 10 and 18 both include the high-k material, the first inter-electrode dielectric 10 has first structure, and the second inter-electrode dielectric 18 has second structure different from the first structure.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使当使用高k材料用于电极间电介质时，也可防止外围晶体管的性能下降。解决方案：存储单元设置有通过第一栅极绝缘膜7形成在第一和第二扩散层之间的第一沟道区上的浮栅电极8，以及形成在浮栅电极8上的控制栅电极2和11 通过第一电极间电介质10.外围晶体管设置有通过第二栅极绝缘膜16A和16B形成在第三和第四扩散层之间的第二沟道区上的下电极17，以及形成在下部电极电介质10上的上电极3和19 电极17穿过第二电极间电介质18.下电极17和上电极3和19通过设置在第二电极间电介质18上的开口电连接在一起。第一和第二电极间电介质10和18 都包括高k材料，第一电极间电介质10具有第一结构，并且第二电极间电介质18具有第二结构dif 与第一个结构不一致。版权所有（C）2009，JPO＆INPIT

25. 发明专利

JP2008311679A Method for setting threshold of semiconductor memory 审中-公开
标题翻译：用于设置半导体存储器阈值的方法
公开(公告)号：JP2008311679A
公开(公告)日：2008-12-25
申请号：JP2008217927
申请日：2008-08-27
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , SAKUI YASUSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To achieve a high-density cell arrangement regarding a cell array having a select gate. SOLUTION: A method for setting a threshold of a semiconductor memory is applied to a semiconductor memory having a plurality of cell units each composed of a selection switching element, having a charge storage layer formed of an insulator, and a memory cell having a charge storage layer formed of an insulator. The selection switching element has a select gate electrode and a second insulating film arranged between the select gate electrode and the charge storage layer. A current generated by electrons is made to flow to the second insulating film when erasing the selection switching element so as to saturate an erasing threshold. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：实现关于具有选择栅极的单元阵列的高密度单元布置。解决方案：一种用于设置半导体存储器的阈值的方法被应用于具有多个单元单元的半导体存储器，所述多个单元单元由选择开关元件组成，所述选择开关元件具有由绝缘体形成的电荷存储层，以及具有由绝缘体形成的电荷存储层。选择开关元件具有选择栅电极和布置在选择栅电极和电荷存储层之间的第二绝缘膜。当擦除选择开关元件以使擦除阈值饱和时，使由电子产生的电流流向第二绝缘膜。版权所有（C）2009，JPO＆INPIT

26. 发明专利

JP2008130676A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2008130676A
公开(公告)日：2008-06-05
申请号：JP2006311789
申请日：2006-11-17
申请人： Toshiba Corp , 株式会社東芝
发明人： TSURUMI DAISUKE , NOGUCHI MITSUHIRO , KOYAMA HARUHIKO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/66825 , H01L29/788
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of preventing an electric field from concentrating so as to improve its reliability. SOLUTION: The nonvolatile semiconductor memory is equipped with two or more memory cell transistors MTs, which are provided with a charge storage layer 3 and a laminated gate containing control gate electrodes 5 and 6 and where current paths are connected in series, a first selection transistor ST1 whose current path is connected to one of the memory cell transistors MTs located at one end of their series connection, and a second selection transistor ST2 whose current path is connected to the other of the memory cell transistors MTs located at the other end of their series connection. The control gate electrodes 5 and 6 have each a configuration in which its upper surface corners are rounded, and the rounded upper surface has a curvature radius of 5 nm or above. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止电场集中以提高其可靠性的非易失性半导体存储器。解决方案：非易失性半导体存储器配备有两个或更多个存储单元晶体管MT，它们设置有电荷存储层3和包含控制栅电极5和6的层叠栅极，其中电流路径串联连接第一选择晶体管ST1，其电流路径连接到位于其串联连接的一端的存储单元晶体管MT之一;以及第二选择晶体管ST2，其电流通路连接到位于另一端的另一个存储单元晶体管MT 其串联连接结束。控制栅极电极5和6各自具有其上表面角圆形的结构，并且圆形上表面具有5nm或更大的曲率半径。版权所有（C）2008，JPO＆INPIT

27. 发明专利

JP2008047283A Data storage system and its setting method 有权
标题翻译：数据存储系统及其设置方法
公开(公告)号：JP2008047283A
公开(公告)日：2008-02-28
申请号：JP2007241540
申请日：2007-09-18
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , AIDA AKIRA
IPC分类号： G11C29/42 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a data storage system and its setting method capable of further reducing a generation rate of a defective bit seen from an external interface. SOLUTION: The system includes: a non-spare area (1n) having a plurality of memory cell blocks and including pages connected to some of these memory cell blocks; a spare area (1s) having a plurality of spare memory cell blocks, the data of which are preliminarily arranged all alike to certain values, and including pages connected to some of these spare memory cell blocks; decision circuits (5, 6, 100) for detecting at least two bits of data error when the data are read out from the pages in the non-spare area (1n) and deciding the number of erroneous bits in the read out pages for every read out page. When the results decided by the decision circuit (100) as to the number of erroneous bits show ≥2 bits, the errors in contents of the read out pages are corrected, then the contents are written into the pages in the spare area (1n). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够进一步降低从外部接口看到的有缺陷的位的生成速率的数据存储系统及其设置方法。解决方案：该系统包括：具有多个存储单元块的非备用区（1n），并且包括连接到这些存储单元块中的一些的页面; 具有多个备用存储单元块的备用区（1s），其数据被预先排列成一定的值，并包括连接到这些备用存储单元块中的一些的页面; 用于当从非备用区域（1n）中的页面读出数据时检测数据错误的至少两位的判定电路（5,6,10），并且为每个读取的页面确定读出页面中的错误位数读出页面。当判定电路（100）对错误位数确定的结果显示≥2位时，校正读出页内容的错误，然后将内容写入备用区（1n）中的页面，。版权所有（C）2008，JPO＆INPIT

28. 发明专利

JP2008010645A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2008010645A
公开(公告)日：2008-01-17
申请号：JP2006179835
申请日：2006-06-29
申请人： Toshiba Corp , 株式会社東芝
发明人： GOMIKAWA KENJI , NOGUCHI MITSUHIRO , AOI TAKAYUKI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7885 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/045
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can improve operating reliability. SOLUTION: The semiconductor memory device is formed on the surface (001) of a semiconductor substrate 1; and is equipped with an n-type first MIS transistor 3 having a charge storage layer FG in which data retention is possible, and a memory cell block 21 including more than 3 of the first MIS transistors 3 in which current paths are connected in series. The direction along a source S to a drain D in the first MIS transistor 3 is parallel to either of the [001] direction and the [010] direction of the semiconductor substrate 1. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供可以提高操作可靠性的半导体存储器件。解决方案：半导体存储器件形成在半导体衬底1的表面（001）上; 并且配备有具有可以进行数据保持的电荷存储层FG的n型第一MIS晶体管3和包括电流路径串联连接的第一MIS晶体管3中的3个以上的存储单元块21的存储单元块21。第一MIS晶体管3中的源极S到漏极D的方向平行于半导体衬底1的[001]方向和[010]方向之一。版权所有（C）2008，JPO＆INPIT

29. 发明专利

JP2007221084A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2007221084A
公开(公告)日：2007-08-30
申请号：JP2006140327
申请日：2006-05-19
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device in which a write characteristic of a memory cell is improved by preventing a threshold of a selection gate transistor from lowering. SOLUTION: The nonvolatile semiconductor storage device having a plurality of NAND strings, wherein each of the NAND strings comprises: a memory cell block to which a plurality of nonvolatile memory cells are serially connected; a first selection gate transistor connected to a data transfer line contact; and a second selection gate transistor connected to a source line contact. The height of the upper surface of an element separation insulating film 24 between an adjacent data transfer line contacts is higher than that of the main surface of a semiconductor substrate 23 in an element region between the first selection gate transistor and data transfer line contact. Alternatively, the height of the upper surface of the element separation insulating film 24 between the adjacent source line contacts is higher than that of the main surface of the semiconductor substrate 23 in an element region between the second selection gate transistor and source line contact. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种通过防止选择栅极晶体管的阈值降低来提高存储单元的写入特性的非易失性半导体存储器件。解决方案：具有多个NAND串的非易失性半导体存储装置，其中每个NAND串包括：多个非易失性存储单元串联连接的存储单元块; 连接到数据传输线触点的第一选择栅极晶体管; 以及连接到源极线接触的第二选择栅极晶体管。在第一选择栅晶体管和数据传输线接触之间的元件区域中，相邻数据传输线触点之间的元件隔离绝缘膜24的上表面的高度高于半导体衬底23的主表面的高度。或者，在第二选择栅极晶体管和源极线接触之间的元件区域中，相邻源极线触点之间的元件隔离绝缘膜24的上表面的高度高于半导体衬底23的主表面的高度。版权所有（C）2007，JPO＆INPIT

30. 发明专利

JP2007220736A Semiconductor device, and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007220736A
公开(公告)日：2007-08-30
申请号：JP2006036869
申请日：2006-02-14
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO TOUSHI , ISHIBASHI SHIGERU , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/823807 , H01L21/823857 , H01L21/823892
摘要： PROBLEM TO BE SOLVED: To prevent fluctuation in threshold voltage and improve short channel effect. SOLUTION: The semiconductor device comprises a first conductive first semiconductor region 11, a second conductive first MIS transistor HV-NMOS formed within the first semiconductor region 11, a second conductive second semiconductor region 14, and a first conductive second MIS transistor LV-PMOS formed within the second semiconductor device 14. A first gate insulating layer 16 of the first MIS transistor HV-NMOS is thicker than the second gate insulating layer 23 of the second MIS transistor LV-PMOS. A profile of a first conductive impurity in a channel region 25 of the second MIS transistor LV-PMOS has a plurality of peaks. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了防止阈值电压的波动，提高短路效应。解决方案：半导体器件包括第一导电第一半导体区域11，形成在第一半导体区域11内的第二导电第一MIS晶体管HV-NMOS，第二导电第二半导体区域14和第一导电第二MIS晶体管LV -PMOS形成在第二半导体器件14内。第一MIS晶体管HV-NMOS的第一栅极绝缘层16比第二MIS晶体管LV-PMOS的第二栅极绝缘层23厚。第二MIS晶体管LV-PMOS的沟道区域25中的第一导电杂质的轮廓具有多个峰。版权所有（C）2007，JPO＆INPIT

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