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21. 发明授权

US06841943B2 Plasma processor with electrode simultaneously responsive to plural frequencies 有权
标题翻译：等离子体处理器，电极同时响应多个频率
公开(公告)号：US06841943B2
公开(公告)日：2005-01-11
申请号：US10180978
申请日：2002-06-27
申请人： Vahid Vahedi , Peter Loewenhardt , Albert Ellingboe , Andras Kuthi , Andreas Fischer
发明人： Vahid Vahedi , Peter Loewenhardt , Albert Ellingboe , Andras Kuthi , Andreas Fischer
IPC分类号： H05H1/46 , C23C16/505 , H01J37/32 , H01L21/3065 , H01J7/24
CPC分类号： H01J37/32082 , H01J37/32165
摘要： A plasma in a vacuum chamber where a workpiece is processed is bounded by a plasma confinement volume including a region between a first electrode simultaneously responsive to power at first and second RF frequencies and a DC grounded second electrode. A DC grounded extension is substantially aligned with the first electrode. A substantial percentage of power at the first frequency is coupled to a path including the first and second electrodes but not the extension while a substantial percentage of power at the second frequency is coupled to a path including the first electrodes and extension, but not the second electrode. Changing the relative powers at the first and second frequencies, as applied to the first electrode, controls DC bias voltage of the first electrode.
摘要翻译：处理工件的真空室中的等离子体由包括第一电极同时响应于第一和第二RF频率的功率的第一电极和直流接地第二电极之间的等离子体约束体积界定。直流接地延伸部基本上与第一电极对准。在第一频率处的相当大的功率百分比被耦合到包括第一和第二电极而不是扩展的路径，而在第二频率处的相当大的功率百分比被耦合到包括第一电极和延伸的路径，而不是第二频率的路径电极。施加到第一电极的第一和第二频率处的相对功率的改变控制第一电极的直流偏置电压。

22. 发明授权

US06653058B2 Methods for reducing profile variation in photoresist trimming 有权
公开(公告)号：US06653058B2
公开(公告)日：2003-11-25
申请号：US09948392
申请日：2001-09-06
申请人： Vahid Vahedi , Yosias Melaku
发明人： Vahid Vahedi , Yosias Melaku
IPC分类号： G03F736
CPC分类号： H01L21/31138 , G03F7/40 , H01L21/0274 , H01L21/0332 , H01L21/0335 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method of removing photoresist material from a semiconductor substrate includes providing a semiconductor substrate having a patterned photoresist mask. A layer comprised of polymer material is formed over the patterned photoresist mask. The layer comprised of polymer material and a portion of the patterned photoresist mask are then removed. The layer comprised of polymer material is preferably formed by introducing a process gas into a plasma environment and is preferably formed with less thickness in a low aspect ratio area relative to a high aspect ratio area.

23. 发明授权

US06218309B1 Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features 有权
标题翻译：在蚀刻浅沟槽隔离特征的同时实现顶部圆整和均匀蚀刻深度的方法
公开(公告)号：US06218309B1
公开(公告)日：2001-04-17
申请号：US09410365
申请日：1999-09-30
申请人： Alan J. Miller , Vahid Vahedi
发明人： Alan J. Miller , Vahid Vahedi
IPC分类号： H01L21311
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/76232
摘要： A method of etching a trench in a silicon layer is disclosed. The silicon layer is disposed below a hard mask layer having a plurality of patterned openings. The etching takes place in a plasma processing chamber. The method includes flowing a first etchant source gas into the plasma processing chamber, forming a first plasma from the first etchant source gas and etching through a first portion of the silicon layer with the first plasma at a first etch rate. The first etch rate being sufficiently slow to form an effective top-rounded attribute in a portion of the trench. The method further includes flowing a second etchant source gas into the plasma processing chamber, forming a second plasma from the second etchant source gas and etching through a second portion of the silicon layer with the second plasma, wherein the etching with the second plasma extends the trench into the silicon layer without unduly damaging the top rounded attribute.
摘要翻译：公开了一种在硅层中蚀刻沟槽的方法。硅层设置在具有多个图案化开口的硬掩模层的下方。蚀刻发生在等离子体处理室中。该方法包括将第一蚀刻剂源气体流入等离子体处理室，从第一蚀刻剂源气体形成第一等离子体，并以第一蚀刻速率用第一等离子体蚀刻硅层的第一部分。第一蚀刻速率足够慢以在沟槽的一部分中形成有效的顶圆属性。该方法还包括使第二蚀刻剂源气体流入等离子体处理室，从第二蚀刻剂源气体形成第二等离子体，并用第二等离子体蚀刻硅层的第二部分，其中用第二等离子体进行的蚀刻将沟槽进入硅层，而不会不适当地损坏顶部圆形属性。

24. 发明授权

US06168690A Methods and apparatus for physical vapor deposition 失效
标题翻译：物理气相沉积的方法和装置
公开(公告)号：US06168690A
公开(公告)日：2001-01-02
申请号：US08939182
申请日：1997-09-29
申请人： Russell F. Jewett , Neil M. Benjamin , Andrew J. Perry , Vahid Vahedi
发明人： Russell F. Jewett , Neil M. Benjamin , Andrew J. Perry , Vahid Vahedi
IPC分类号： C23C1434
CPC分类号： H01J37/321 , C23C14/32 , C23C14/34 , C23C14/3407 , H01J37/34
摘要： The invention relates to an improved sputter target that is a combination sputter target and induction antenna. In one embodiment, when the sputter target is energized sputter material particles are sputtered away from the sputter target and a plasma is induced. In another embodiment, the sputter target is energized by an energy source. In yet another embodiment, the energy source includes a bias power supply and an induction power supply. The bias power supply applies a potential to the sputter target relative to an object. The induction power supply applies a current to the sputter target. The potential and the current promote the sputtering away of the sputter target, the formation of the plasma and the anisotropic distribution of the sputtered material particles.
摘要翻译：本发明涉及一种改进的溅射靶，其是溅射靶和感应天线的组合。在一个实施例中，当溅射靶被激发时，溅射材料颗粒被溅射离开溅射靶，并且引发等离子体。在另一个实施例中，溅射靶被能量源激励。在另一个实施例中，能量源包括偏置电源和感应电源。偏置电源对溅射靶相对于物体施加电位。感应电源向溅射靶施加电流。电势和电流促使溅射靶的溅射，等离子体的形成和溅射的材料颗粒的各向异性分布。

25. 发明授权

US5913140A Method for reduction of plasma charging damage during chemical vapor deposition 失效
标题翻译：在化学气相沉积期间减少等离子体充电损伤的方法
公开(公告)号：US5913140A
公开(公告)日：1999-06-15
申请号：US780027
申请日：1996-12-23
申请人： Gregory A. Roche , David T. Hodul , Vahid Vahedi
发明人： Gregory A. Roche , David T. Hodul , Vahid Vahedi
IPC分类号： C23C16/04 , C23C16/517 , H01L21/316 , H01L21/762
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/517 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： A graded gap fill process in which, in a high density plasma processing chamber, an insulating layer is deposited on a substrate without causing plasma charge-related damage to the substrate. The insulating layer is disposed above a first layer having trenches formed therein and below a subsequently deposited second layer. A protection layer is first deposited above the first layer using a first set of deposition parameters. This protection layer coats a surface of the first layer in a substantially conformal manner without forming voids in the trenches. A fill layer is then deposited above the protection layer using a second set of deposition parameters. The first set of deposition parameters is selected to reduce plasma charge-related damage relative to the second set of deposition parameters. The combination of the protection layer and the fill layer sufficiently electrically isolates the first layer from the second layer.
摘要翻译：梯度间隙填充工艺，其中在高密度等离子体处理室中，绝缘层沉积在衬底上，而不会对衬底造成等离子体电荷相关损伤。绝缘层设置在其上形成有沟槽并在随后沉积的第二层下面的第一层之上。首先使用第一组沉积参数将保护层沉积在第一层之上。该保护层以基本上共形的方式涂覆第一层的表面，而不在沟槽中形成空隙。然后使用第二组沉积参数在保护层上方沉积填充层。选择第一组沉积参数以相对于第二组沉积参数来减少等离子体电荷相关的损伤。保护层和填充层的组合使第一层与第二层充分电隔离。

26. 再颁专利

USRE39534E1 Method and apparatus to calibrate a semi-empirical process simulator 有权
标题翻译：用于校准半经验过程模拟器的方法和装置
公开(公告)号：USRE39534E1
公开(公告)日：2007-03-27
申请号：US10302567
申请日：2002-11-22
申请人： David Cooperberg , Richard A. Gottscho , Vahid Vahedi
发明人： David Cooperberg , Richard A. Gottscho , Vahid Vahedi
IPC分类号： G05B13/02
摘要： A method and apparatus for calibrating a semi-empirical process simulator used to determine process values in a plasma process for creating a desired surface profile on a process substrate includes providing a test model which captures all mechanisms responsible for profile evolution in terms of a set of unknown surface parameters. A set Sets of test conditions processes is are derived for which the profile evolution is governed by only a limited number of parameters. For each set of test conditions process, model test values are selected and a test substrate is substrates are actually subjected to a the test process processes defined by the test values , thereby creating a test surface profile profiles. The test values are used to generate an approximate profile prediction predictions and are adjusted to minimize the discrepancy between the test surface profile profiles and the approximate profile prediction predictions, thereby providing a final model of the profile evolution in terms of the process values.
摘要翻译：用于校准用于确定等离子体工艺中的工艺值以用于在工艺衬底上创建所需表面轮廓的半经验过程模拟器的方法和装置包括提供测试模型，该测试模型根据一组未知表面参数。一组集合的测试条件过程被导出，其中简档演化仅由有限数量的参数来管理。对于每组测试条件过程，选择模型测试值，并且测试衬底实际上经受由测试值定义的测试过程过程，从而产生测试表面轮廓。测试值用于生成近似轮廓预测预测，并进行调整，以最小化测试曲面轮廓轮廓和近似轮廓预测预测之间的差异，从而根据过程值提供轮廓演变的最终模型。

27. 发明授权

US06994769B2 In-situ cleaning of a polymer coated plasma processing chamber 有权
标题翻译：聚合物涂层等离子体处理室的原位清洗
公开(公告)号：US06994769B2
公开(公告)日：2006-02-07
申请号：US10881112
申请日：2004-06-29
申请人： Harmeet Singh , John E. Daugherty , Vahid Vahedi , Saurabh J. Ullal
发明人： Harmeet Singh , John E. Daugherty , Vahid Vahedi , Saurabh J. Ullal
IPC分类号： C23F1/00
CPC分类号： H01J37/32862 , C23C16/4404 , C23C16/4405 , H01J37/321 , Y10S134/902 , Y10S438/905
摘要： An apparatus configured to remove chamber deposits between process operations is provided. The processing chamber includes a top electrode in communication with a power supply. A processing chamber defined within a base, a sidewall extending from the base, and a top disposed on the sidewall is provided. The processing chamber has an outlet enabling removal of fluids within the processing chamber. The processing chamber includes a substrate support and an inner surface of the processing chamber defined by the base, the sidewall and the top. The inner surface is coated with a fluorine containing polymer coating. The fluorine containing polymer coating is configured to release fluorine upon creation of an oxygen plasma in the processing chamber to remove a residue deposited on the fluorine containing polymer coating. The residue was deposited on the polymer coating from a processing operation performed in the processing chamber.
摘要翻译：提供一种被配置为在处理操作之间去除室沉积物的装置。处理室包括与电源连通的顶部电极。设置在基座内的处理室，从基座延伸的侧壁和设置在侧壁上的顶部。处理室具有能够去除处理室内的流体的出口。处理室包括基板支撑件和由基座，侧壁和顶部限定的处理室的内表面。内表面涂有含氟聚合物涂层。含氟聚合物涂层被配置为在处理室中产生氧等离子体时释放氟以除去沉积在含氟聚合物涂层上的残余物。残留物从处理室中进行的处理操作沉积在聚合物涂层上。

28. 发明申请

US20050278057A1 Enhanced process and profile simulator algorithms 有权
标题翻译：增强的过程和轮廓模拟器算法
公开(公告)号：US20050278057A1
公开(公告)日：2005-12-15
申请号：US10932926
申请日：2004-09-01
申请人： David Cooperberg , Vahid Vahedi
发明人： David Cooperberg , Vahid Vahedi
IPC分类号： G06F19/00 , H01J37/32
CPC分类号： H01J37/32935 , H01J37/321 , H01J37/32174
摘要： A method for enhancing a process and profile simulator algorithm predicts the surface profile that a given plasma process will create. An energetic particle is first tracked. The ion fluxes produced by the energetic particle are then recorded. A local etch rate and a local deposition rate are computed from neutral fluxes, surface chemical coverage, and surface material type that are solved simultaneously.
摘要翻译：用于增强过程和轮廓模拟器算法的方法预测给定等离子体过程将产生的表面轮廓。首先跟踪一个精力充沛的粒子。然后记录由能量粒子产生的离子通量。局部蚀刻速率和局部沉积速率由同时求解的中性焊剂，表面化学覆盖度和表面材料类型计算。

29. 发明授权

US06804572B1 Enhanced process and profile simulator algorithms 有权
标题翻译：增强的过程和轮廓模拟器算法
公开(公告)号：US06804572B1
公开(公告)日：2004-10-12
申请号：US09609593
申请日：2000-06-30
申请人： David Cooperberg , Vahid Vahedi
发明人： David Cooperberg , Vahid Vahedi
IPC分类号： G05B1302
CPC分类号： H01J37/32935
摘要： A method enhances a process and profile simulator algorithm to predict the surface profile that a given plasma process will create. The method first tracks an energetic particle and then records the ion fluxes produced by the energetic particle. A local etch rate and a local deposition rate are computed from neutral fluxes, surface chemical coverage, and surface material type that are solved simultaneously.
摘要翻译：一种方法增强了过程和轮廓模拟器算法来预测给定等离子体过程将产生的表面轮廓。该方法首先跟踪能量粒子，然后记录由能量粒子产生的离子通量。局部蚀刻速率和局部沉积速率由同时求解的中性焊剂，表面化学覆盖度和表面材料类型计算。

30. 发明授权

US06489245B1 Methods for reducing mask erosion during plasma etching 有权
标题翻译：在等离子体蚀刻期间减少掩模侵蚀的方法
公开(公告)号：US06489245B1
公开(公告)日：2002-12-03
申请号：US09610303
申请日：2000-07-05
申请人： Jaroslaw W. Winniczek , Vahid Vahedi
发明人： Jaroslaw W. Winniczek , Vahid Vahedi
IPC分类号： H01L21302
CPC分类号： H01J37/32623 , H01J37/32706
摘要： A method for reducing erosion of a mask while etching a feature in a first layer underlying the mask is disclosed. The first layer is disposed on a substrate, with the substrate being positioned on a chuck within in a plasma processing chamber. The method includes flowing an etchant source gas into the plasma processing chamber and forming a plasma from the etchant source gas. The method further includes pulsing an RF power source at a predefined pulse frequency to provide pulsed RF power to the chuck. The pulsed RF power has a first frequency and alternates between a high power cycle and a low power cycle at the pulse frequency. The pulse frequency is selected to be sufficiently low to cause polymer to be deposited on the mask during the low power cycle.
摘要翻译：公开了一种在蚀刻掩模下面的第一层中的特征时减少掩模侵蚀的方法。第一层设置在基板上，其中基板位于等离子体处理室内的卡盘上。该方法包括将蚀刻剂源气体流入等离子体处理室并从蚀刻剂源气体形成等离子体。该方法还包括以预定的脉冲频率脉冲地将RF功率脉冲给卡盘提供脉冲的RF功率。脉冲RF功率具有第一频率，并且在脉冲频率下在高功率周期和低功率周期之间交替。选择脉冲频率足够低以在低功率循环期间使聚合物沉积在掩模上。

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