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21. 发明授权

US5159194A Method and apparatus for mass spectrometry 失效
标题翻译：用于质谱分析的方法和装置
公开(公告)号：US5159194A
公开(公告)日：1992-10-27
申请号：US756290
申请日：1991-09-06
申请人： Philip Marriott , Anthony M. Jones , Robert S. Taylor
发明人： Philip Marriott , Anthony M. Jones , Robert S. Taylor
IPC分类号： G01N27/62 , H01J49/02 , H01J49/30
CPC分类号： H01J49/022
摘要： A method of mass spectrometry and a mass spectrometer for the analysis of a sample, the mass spectrometer comprising means for producing ions from the sample and a magnetic sector for analyzing the ions, wherein the magnetic field of the magnetic sector is generated by passage of a magnet current controlled by a digital control signal representative of a sequence of integers generated by a computer. According to the invention, means are provided for generating the magnet current in exponential relation to the sequence of integers. In contrast to prior spectrometers, the invention provides peak switching and mass selection across the mass range with a constant number of integer steps per mass peak, thereby facilitating the digital selection of any particular mass peak, particularly those at low mass.

22. 发明授权

US4843674A Sweep mop pad holder 失效
标题翻译：清扫拖把垫架
公开(公告)号：US4843674A
公开(公告)日：1989-07-04
申请号：US243289
申请日：1988-09-09
申请人： Anthony M. Jones
发明人： Anthony M. Jones
IPC分类号： A47L13/258
CPC分类号： A47L13/258
摘要： A collapsible mop pad holder comprises two opposite end leaves pivotally mounted on a central support which is connectible to a handle, and a catch operative to latch the end leaves in an erected condition. The catch comprises a latch member pivotally mounted on one of the leaves and depressible from a latching position, in which it engages the other leaf to latch both leaves together and thus maintains the erected condition of the holder, to an unlatching position in which it is retained until the mop pad holder is collapsed. The arrangement is such that on re-erection of the mop pad holder the latch member automatically re-assumes the latching position.

23. 发明申请

US20190087876A1 User Engagement Display System 审中-公开
公开(公告)号：US20190087876A1
公开(公告)日：2019-03-21
申请号：US16195165
申请日：2018-11-19
申请人： Anthony M. Jones
发明人： Anthony M. Jones
IPC分类号： G06Q30/02 , G06F3/0481 , G06F16/958 , G06F16/9535 , G06F3/0484
摘要： Disclosed embodiments include a consumer display system that may include the use of a main gauge, sometimes resembling a digital gasoline gauge of a vehicle, such that the main gauge displays an analog and/or digital value to comport with an overall score derived from user input into a plurality of categories.

24. 发明申请

US20160364775A1 User Engagement Display System 审中-公开
标题翻译：用户参与显示系统
公开(公告)号：US20160364775A1
公开(公告)日：2016-12-15
申请号：US15249004
申请日：2016-08-26
申请人： Anthony M. Jones
发明人： Anthony M. Jones
IPC分类号： G06Q30/02 , G06F17/30 , G06F3/0481
CPC分类号： G06Q30/0282 , G06F3/04817 , G06F16/26 , G06F16/9535 , G06F16/958
摘要： Disclosed embodiments include a consumer display system that may include the use of a main gauge, sometimes resembling a digital gasoline gauge of a vehicle, such that the main gauge displays an analog and/or digital value to comport with an overall score derived from user input into a plurality of categories.
摘要翻译：公开的实施例包括消费者显示系统，其可以包括使用主计量器，有时类似于车辆的数字汽油计，使得主计量器显示模拟和/或数字值以与来自用户输入的总得分相匹配分成多个类别。

25. 发明授权

US06171407B2 Ventilation fixture and method of using same 失效
标题翻译：通风夹具及其使用方法
公开(公告)号：US06171407B2
公开(公告)日：2001-01-09
申请号：US09415075
申请日：1999-10-12
申请人： David J. Rackoski , Anthony M. Jones
发明人： David J. Rackoski , Anthony M. Jones
IPC分类号： B08B1300
CPC分类号： B08B15/007
摘要： An apparatus and method are provided for removing gases produced during off-service cleaning of a processing chamber which operates under vacuum in a wafer fabrication tool. The apparatus includes a ventilation fixture providing a manifold having an internal cavity in fluid communication with a source of vacuum and at least one intake aperture, and a quick disconnect fitting connected to the source of vacuum and in fluid communication with the internal cavity. The manifold is portable and located adjacent to the processing chamber during cleaning.
摘要翻译：提供了一种用于去除在晶片制造工具中在真空下操作的处理室的非工作状态清洁期间产生的气体的装置和方法。该设备包括通风夹具，其提供具有与真空源和至少一个进气孔流体连通的内腔的歧管，以及连接到真空源并与内腔流体连通的快速断开配件。歧管是便携式的，并且在清洁期间位于处理室附近。

26. 发明授权

US5617458A Clock divider 失效
标题翻译：时钟分频器
公开(公告)号：US5617458A
公开(公告)日：1997-04-01
申请号：US567555
申请日：1995-12-05
申请人： Anthony M. Jones , David A. Barnes
发明人： Anthony M. Jones , David A. Barnes
IPC分类号： G06F1/08 , H03K5/15 , H03H11/26
CPC分类号： H03K5/15026 , G06F1/08
摘要： The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.
摘要翻译：本发明公开了一种与L个计数器结合实现L相时钟的方法和装置，其中L是一个整数，以L可缩放的频率进行计数。

27. 发明授权

US5596517A Method and arrangement for transformation of signals from a frequency to a time domain 失效
公开(公告)号：US5596517A
公开(公告)日：1997-01-21
申请号：US400722
申请日：1995-03-07
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.

28. 发明授权

US5594678A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5594678A
公开(公告)日：1997-01-14
申请号：US400723
申请日：1995-03-07
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT或逆离散余弦变换方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT + E，rad 2 + EE，并且奇数输入字在公共处理步骤中处理之前成对地相加。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地向上扩展2ROOT + E，rad 2 + EE的因子。通过强制这些位为“1”或“0”可选地调整一些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

29. 发明授权

US5455522A Programmable logic output driver 失效
标题翻译：可编程逻辑输出驱动器
公开(公告)号：US5455522A
公开(公告)日：1995-10-03
申请号：US82264
申请日：1993-06-24
申请人： Anthony M. Jones
发明人： Anthony M. Jones
IPC分类号： H03K17/04 , H03K17/16 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018585 , H03K19/0005 , H03K19/00361 , H03K19/00384
摘要： A programmable logic output driver includes a bias generator (100), a current mirror (200) and an output stage (300), there being a digital programming feature to maintain the output voltage slew rate at an acceptable value for either high or low values of load capacitances. The driver is programmable and can maintain a constant value of driver output resistance in the circumstances where the load voltage approaches the full swing logic voltage. In the preferred embodiment, the programmed output resistance is independent of variations in process, temperature and VDD supply voltage. TTL loads are driven with the minimum amount of required output current. Because of the constant resistance, the driver supplies a specified amount of current to the load even when the load is pulled down to a specified voltage. The resistance value is substantially the highest value possible consistent with providing a required minimum load drive current and the resistive damping of the output RLC circuit is maximized so that voltage "kick" or "undershoot" is held to a minimum.
摘要翻译：可编程逻辑输出驱动器包括偏置发生器（100），电流镜（200）和输出级（300），存在数字编程特征，以将输出电压转换速率保持在高或低值的可接受值的负载电容。驱动器是可编程的，并且可以在负载电压接近全摆幅逻辑电压的情况下保持驱动器输出电阻的恒定值。在优选实施例中，编程的输出电阻与工艺，温度和VDD电源电压的变化无关。 TTL负载以最小量的所需输出电流驱动。由于电阻恒定，即使负载下拉到指定电压，驱动器也会向负载提供规定量的电流。电阻值基本上是与提供所需的最小负载驱动电流一致的最高值，并且输出RLC电路的电阻性阻尼最大化，使得电压“踢”或“下冲”保持最小。

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