专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06228663B1 Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength 失效
标题翻译：使用栅极绝缘体厚度和沟道长度形成半导体器件以控制驱动电流强度的方法
公开(公告)号：US06228663B1
公开(公告)日：2001-05-08
申请号：US08994107
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford , Anthony J. Toprac
发明人： Mark I. Gardner , H. Jim Fulford , Anthony J. Toprac
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28167 , H01L21/28194 , H01L22/20 , H01L29/42364 , H01L29/42376 , Y10S148/162 , Y10S438/945
摘要： A semiconductor device having a controlled drive current strength is produced by varying gate electrode length to accommodate any variation in insulating layer thickness from a desired value. After formation of the gate insulating layer on a substrate, the thickness is measured and compared to a desired value. Based on any differences between the measured and desired values, the length of the gate electrode is determined in order to counteract the variation in gate insulating layer thickness. This results in a change in channel length that counteracts the effect of the variation in insulating layer thickness on the drive current strength. The present process permits close control over the drive current strength of semiconductor devices. This also can provide decreased variation within and between lots and corresponding increases in productivity.
摘要翻译：具有受控的驱动电流强度的半导体器件通过改变栅电极长度来产生，以适应绝缘层厚度的任何变化与期望值。在基板上形成栅极绝缘层之后，测量厚度并将其与期望值进行比较。基于测量值和期望值之间的任何差异，确定栅电极的长度以抵消栅极绝缘层厚度的变化。这导致沟道长度的改变，其抵消了绝缘层厚度变化对驱动电流强度的影响。本方法允许密切控制半导体器件的驱动电流强度。这也可以在批次之间和之间提供减小的变化，并且相应地提高生产率。

22. 发明授权

US06979878B1 Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites 失效
标题翻译：隔离结构在隔离槽的顶角处注入硅原子填充空位和间隙位置
公开(公告)号：US06979878B1
公开(公告)日：2005-12-27
申请号：US09217213
申请日：1998-12-21
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76237
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在半导体衬底上形成电介质掩模层。然后通过掩模层形成开口。在开口内的掩模层的侧壁上形成一对电介质隔离物。然后在电介质间隔物之间的半导体衬底中蚀刻沟槽。然后在沟槽的壁和基底上热生长第一介电层。将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。然后将硅原子和/或势垒原子（例如氮原子）注入非常靠近沟槽隔离结构的有源区的多个区域中。

23. 发明授权

US06743688B1 High performance MOSFET with modulated channel gate thickness 失效
标题翻译：具有调制通道栅极厚度的高性能MOSFET
公开(公告)号：US06743688B1
公开(公告)日：2004-06-01
申请号：US09002964
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/265 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/518 , H01L29/66553 , H01L29/66583 , H01L29/78 , Y10S438/981
摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
摘要翻译：具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。优选地，通过将栅极区域暴露于氧气环境来生长栅极氧化物。氮注入抑制氧气环境中的二氧化硅生长速率。因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。可以沉积栅极氧化物层而不是生长栅极氧化物层。在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。然后可以注入半导体衬底以形成掺杂的漏极和源极区域。然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。

24. 发明授权

US06451657B1 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant 失效
标题翻译：具有由横向扩散的氮植入物限定的超短沟道长度的晶体管
公开(公告)号：US06451657B1
公开(公告)日：2002-09-17
申请号：US09781044
申请日：2001-02-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , Y10S257/90
摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.
摘要翻译：公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。在轻掺杂的半导体衬底上形成栅氧化层。然后在栅极氧化物层上沉积栅极导体层。栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。热退火降低了无氮区域的宽度。然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。

25. 发明授权

US06281132B1 Device and method for etching nitride spacers formed upon an integrated circuit gate conductor 有权
标题翻译：用于蚀刻形成在集成电路栅极导体上的氮化物间隔物的装置和方法
公开(公告)号：US06281132B1
公开(公告)日：2001-08-28
申请号：US09167622
申请日：1998-10-06
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L213065
CPC分类号： H01L21/31116
摘要： A dry etch method is presented wherein a semiconductor substrate is introduced between a first electrode and a second electrode maintained within a reaction chamber. In this method, a main etch step is performed in which a first quantity of low frequency power is applied to the pair of electrodes from an RF power source. A first gas flow is circulated through the reaction chamber during the application of power. This first gas flow includes a first argon flow, a first oxygen flow, and a first fluorocarbon flow. Applying the first quantity of low frequency power creates a first plasma for etching a portion of a nitride layer arranged above the semiconductor substrate.
摘要翻译：提出了一种干蚀刻方法，其中将半导体衬底引入到保持在反应室内的第一电极和第二电极之间。在该方法中，执行主要蚀刻步骤，其中从RF电源向第一对电极施加第一数量的低频功率。在施加电力期间，第一气流在反应室中循环。该第一气流包括第一氩气流，第一氧气流和第一碳氟化合物流。施加第一量的低频功率产生第一等离子体，用于蚀刻布置在半导体衬底上方的氮化物层的一部分。

26. 发明授权

US06268634B1 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant 失效
标题翻译：具有由横向扩散的氮植入物限定的超短沟道长度的晶体管
公开(公告)号：US06268634B1
公开(公告)日：2001-07-31
申请号：US09178225
申请日：1998-10-23
申请人： Mark I. Gardner , H. Jim Eulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Eulford, Jr. , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L21/28132 , Y10S257/90
摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.
摘要翻译：公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。在轻掺杂的半导体衬底上形成栅氧化层。然后在栅极氧化物层上沉积栅极导体层。栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。热退火降低了无氮区域的宽度。然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。

27. 发明授权

US06258646B1 CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof 有权
标题翻译： CMOS集成电路和用于在注入PMOS晶体管区域之前注入NMOS晶体管区域以优化其热扩散率的方法
公开(公告)号：US06258646B1
公开(公告)日：2001-07-10
申请号：US09149631
申请日：1998-09-08
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , Y10S257/90
摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.
摘要翻译：提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

28. 发明授权

US06248252B1 Method of fabricating sub-micron metal lines 有权
标题翻译：制造亚微米金属线的方法
公开(公告)号：US06248252B1
公开(公告)日：2001-06-19
申请号：US09256541
申请日：1999-02-24
申请人： Thien T. Nguyen , Mark I. Gardner
发明人： Thien T. Nguyen , Mark I. Gardner
IPC分类号： C23F100
CPC分类号： C23F4/00 , H01L21/32136 , H01L21/76838
摘要： Methods of fabricating interconnects of aluminum and aluminum alloys are provided. In one aspect, a method is provided for fabricating an interconnect of aluminum-containing material on a surface. A layer of aluminum-containing material is deposited on the surface. The layer of aluminum-containing material is masked with selected portions thereof left exposed. A first etch of the exposed portions is performed in a plasma ambient containing BCl3, Cl2, N2 and CF4 to establish a plurality of trenches having inwardly sloping sidewalls. An overetch of the exposed portions is performed to the surface in a plasma ambient. High aspect ratio lines may be formed with sloped sidewalls that facilitate subsequent interlevel dielectric formation.
摘要翻译：提供制造铝和铝合金互连的方法。在一个方面，提供了一种用于在表面上制造含铝材料的互连的方法。一层含铝材料沉积在表面上。含铝材料层被掩盖，其中所选择的部分露出。暴露部分的第一蚀刻在含有BCl 3，Cl 2，N 2和CF 4的等离子体环境中进行，以建立具有向内倾斜侧壁的多个沟槽。在等离子体环境中对表面进行暴露部分的过蚀刻。高纵横比线可以形成有倾斜的侧壁，其有助于随后的层间电介质形成。

29. 发明授权

US06245652B1 Method of forming ultra thin gate dielectric for high performance semiconductor devices 有权
标题翻译：形成用于高性能半导体器件的超薄栅极电介质的方法
公开(公告)号：US06245652B1
公开(公告)日：2001-06-12
申请号：US09598531
申请日：2000-06-21
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
IPC分类号： H01L213205
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention is directed to a semiconductor device having an ultra thin, reliable gate dielectric and a method for making same. In one illustrative embodiment, the present method comprises forming a first layer of nitrogen doped silicon dioxide above a semiconducting substrate, reducing the thickness of the first layer, forming a second layer comprised of a material having a dielectric constant greater than seven above the first layer of silicon dioxide. The method further comprises forming a third layer comprised of a gate conductor material above the second layer, and patterning the first, second and third layers to define a gate conductor and a composite gate dielectric comprised of the first and second layers, and forming at least one source/drain region. The semiconductor device has a composite gate dielectric comprised of a first process layer comprised of a nitrogen doped oxide and a second process layer comprised of a material having a dielectric constant greater than seven. The device further comprises a gate conductor positioned above the composite gate dielectric, and at least one source/drain region formed in the substrate.
摘要翻译：本发明涉及具有超薄，可靠的栅极电介质的半导体器件及其制造方法。在一个说明性实施例中，本方法包括在半导体衬底上形成氮掺杂二氧化硅的第一层，减小第一层的厚度，形成第二层，第二层由介电常数大于第一层以上的材料构成的二氧化硅。该方法还包括在第二层上形成由栅极导体材料构成的第三层，以及对第一层，第二层和第三层进行构图以限定由第一层和第二层构成的栅极导体和复合栅极电介质，并形成至少一个源/漏区。该半导体器件具有复合栅极电介质，该复合栅极电介质由包含氮掺杂氧化物的第一工艺层和由介电常数大于7的材料构成的第二工艺层组成。该器件还包括位于复合栅极电介质上方的栅极导体，以及形成在衬底中的至少一个源极/漏极区。

30. 发明授权

US06232637B1 Semiconductor fabrication having multi-level transistors and high density interconnect therebetween 有权
标题翻译：具有多电平晶体管和其间的高密度互连的半导体制造
公开(公告)号：US06232637B1
公开(公告)日：2001-05-15
申请号：US09249954
申请日：1999-02-12
申请人： Mark I. Gardner , Daniel Kadosh
发明人： Mark I. Gardner , Daniel Kadosh
IPC分类号： H01L31036
CPC分类号： H01L27/0688 , H01L21/8221
摘要： An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.
摘要翻译：提供了一种集成电路制造工艺，其中可以形成高掺杂多晶硅结构。升高的结构可以用作完全在升高的多晶硅内部和之上形成的晶体管的结区域。升高的结构释放了用于附加晶体管和/或横向互连的下层衬底内的空间，其益处是促进集成电路内的更高的堆积密度。提供晶体管，其包括在一对结之间间隔开的栅极导体。在晶体管两端沉积初级层间电介质。在初级层间电介质的上表面的选择部分内形成多晶硅结构。多晶硅结构是距离晶体管的上方和横向距离之间的间隔距离。将掺杂剂注入到多晶硅结构中。次级层间电介质沉积在初级层间电介质和掺杂多晶硅结构之间。选择部分初级和次级层间电介质然后被去除以暴露出一个结点，并且掺杂多晶硅结构的一部分布置在该结附近。通过在去除的部分内沉积导电材料，在结和多晶硅结构之间连续地形成互连。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式