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21. 发明申请

US20050280069A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050280069A1
公开(公告)日：2005-12-22
申请号：US10923831
申请日：2004-08-24
申请人： Ichiro Mizushima , Tetsuya Kai , Yoshio Ozawa , Kouichi Muraoka , Shinichi Nakamura
发明人： Ichiro Mizushima , Tetsuya Kai , Yoshio Ozawa , Kouichi Muraoka , Shinichi Nakamura
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/512
摘要： A semiconductor device using a high dielectric constant insulator having reduced leak current as an interelectrode insulator is provided by comprising a first insulator formed on a semiconductor substrate, a first gate electrode formed on the first insulator, a second gate electrode formed above the first gate electrode, and a second crystallized insulator formed between the first gate electrode and the second gate electrode.
摘要翻译：通过包括形成在半导体衬底上的第一绝缘体，形成在第一绝缘体上的第一栅极电极和形成在第一栅电极之上的第二栅极电极，提供使用具有减小的漏电流的高介电常数绝缘体作为电极间绝缘体的半导体器件以及形成在第一栅电极和第二栅电极之间的第二结晶绝缘体。

22. 发明授权

US08637915B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08637915B2
公开(公告)日：2014-01-28
申请号：US13007258
申请日：2011-01-14
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

23. 发明授权

US08604536B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604536B2
公开(公告)日：2013-12-10
申请号：US12406841
申请日：2009-03-18
申请人： Katsuyuki Sekine , Yoshio Ozawa
发明人： Katsuyuki Sekine , Yoshio Ozawa
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/66833
摘要： A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.
摘要翻译：半导体器件包括存储单元晶体管，其包括设置在半导体衬底上的第一下绝缘膜，设置在第一下绝缘膜上的第一中间绝缘膜，设置在第一中间绝缘膜上的第一上绝缘膜和第一栅极设置在第一上绝缘膜上的电极和设置在半导体衬底上的第二下绝缘膜的选择晶体管，设置在第二下绝缘膜上的第二中间绝缘膜，设置在第二中间绝缘膜上的第二上绝缘膜以及设置在第二上绝缘膜上的第二栅电极，其中第二中间绝缘膜的阱密度低于第一中间绝缘膜的陷阱密度。

24. 发明授权

US08324679B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08324679B2
公开(公告)日：2012-12-04
申请号：US13430153
申请日：2012-03-26
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

25. 发明申请

US20120282773A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120282773A1
公开(公告)日：2012-11-08
申请号：US13487280
申请日：2012-06-04
申请人： Isao Kamioka , Junichi Shiozawa , Ryu Kato , Yoshio Ozawa
发明人： Isao Kamioka , Junichi Shiozawa , Ryu Kato , Yoshio Ozawa
IPC分类号： H01L21/302
CPC分类号： H01L29/7881 , H01L21/76208 , H01L27/11521 , H01L29/66825
摘要： In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.
摘要翻译：在一个实施例中，制造半导体器件的方法包括在半导体衬底上形成其上表面和侧表面被暴露的导电膜和上表面暴露的绝缘膜。该方法还包括通过施加微波，射频波或电子回旋共振等将由等离子体产生的等离子体中包含的氧化离子或氮化离子供应到导电膜的暴露侧表面和绝缘膜的暴露的上表面对半导体衬底施加预定的电压，从而进行导电膜的暴露的侧表面和绝缘膜的暴露的上表面的各向异性氧化或各向异性氮化。

26. 发明授权

US08304352B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08304352B2
公开(公告)日：2012-11-06
申请号：US13051031
申请日：2011-03-18
申请人： Masayuki Tanaka , Kazuhiro Matsuo , Yoshio Ozawa
发明人： Masayuki Tanaka , Kazuhiro Matsuo , Yoshio Ozawa
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28282 , H01L27/11568 , H01L27/11582
摘要： According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.
摘要翻译：根据一个实施例，提供一种制造半导体器件的方法，包括通过氮化作为主要成分的含有硅的半导体区域的下面的区域的表面和以硅和氧为主要的绝缘区域来形成氮化物膜并且与半导体区域相邻，相对于氮化物膜进行氧化，将形成在绝缘区域上的氮化物膜的一部分转换为氧化膜，并且使形成在该半导体层上的氮化膜的一部分半导体区域作为电荷存储绝缘膜的至少一部分，在电荷存储绝缘膜上形成块绝缘膜，并在块绝缘膜上形成栅极电极膜。

27. 发明授权

US08198159B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08198159B2
公开(公告)日：2012-06-12
申请号：US12054089
申请日：2008-03-24
申请人： Masayuki Tanaka , Yoshio Ozawa , Hirokazu Ishida , Katsuaki Natori , Seiji Inumiya
发明人： Masayuki Tanaka , Yoshio Ozawa , Hirokazu Ishida , Katsuaki Natori , Seiji Inumiya
IPC分类号： H01L21/324 , H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译：半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上门和控制门。

28. 发明申请

US20120094476A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120094476A1
公开(公告)日：2012-04-19
申请号：US13051031
申请日：2011-03-18
申请人： Masayuki TANAKA , Kazuhiro Matsuo , Yoshio Ozawa
发明人： Masayuki TANAKA , Kazuhiro Matsuo , Yoshio Ozawa
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L27/11568 , H01L27/11582
摘要： According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.
摘要翻译：根据一个实施例，提供一种制造半导体器件的方法，包括通过氮化作为主要成分的含有硅的半导体区域的下面的区域的表面和以硅和氧为主要的绝缘区域来形成氮化物膜并且与半导体区域相邻，相对于氮化物膜进行氧化，将形成在绝缘区域上的氮化物膜的一部分转换为氧化膜，并且使形成在该半导体层上的氮化膜的一部分半导体区域作为电荷存储绝缘膜的至少一部分，在电荷存储绝缘膜上形成块绝缘膜，并在块绝缘膜上形成栅极电极膜。

29. 发明申请

US20110248329A1 METHOD OF MANUFACTURING A NON-VOLATILE NAND MEMORY SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：制造非易失性NAND存储器半导体集成电路的方法
公开(公告)号：US20110248329A1
公开(公告)日：2011-10-13
申请号：US13164946
申请日：2011-06-21
申请人： Toshitake Yaegashi , Yoshio Ozawa
发明人： Toshitake Yaegashi , Yoshio Ozawa
IPC分类号： H01L27/105 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.
摘要翻译：半导体集成电路器件包括：第一，第二栅电极，第一，第二扩散层，电连接到第一扩散层的接触电极;第一绝缘膜，其在第一和第二栅电极之间具有凹入部分，并且不含氮作为主要成分，形成在第一绝缘膜上并且不含氮作为主要成分的第二绝缘膜和形成在第一扩散层上的第三绝缘膜，第一栅电极，第二扩散层和第二栅电极，第二绝缘膜设置在部分区域之间。形成第二绝缘膜以填充凹部，并且第一和第二栅电极之间的部分具有至少包含第一绝缘膜和第二绝缘膜的多层结构。

30. 发明授权

US07999304B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07999304B2
公开(公告)日：2011-08-16
申请号：US12026942
申请日：2008-02-06
申请人： Yoshio Ozawa , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
发明人： Yoshio Ozawa , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/512 , H01L29/513 , H01L29/66825 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.
摘要翻译：半导体器件包括半导体衬底和非易失性存储单元，每个单元包括具有沟道长度和沟道宽度的沟道区，隧道绝缘膜，浮栅电极，控制栅电极，电极间绝缘在浮置控制栅电极和控制栅极电极的侧壁表面之间的电极侧壁绝缘膜，电极侧壁绝缘膜包括具有第一和第二介电常数的第一和第二绝缘膜，所述第一介电常数高于所述第二介电常数，所述第二介电常数高于氮化硅膜的介电常数，所述第一绝缘膜位于所述浮动栅极和控制栅电极之间的面对区域的中心区域中，第二绝缘区域位于面对区域的两端区域中并从两端口突出 ons。

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