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21. 发明授权

US5537356A Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5537356A
公开(公告)日：1996-07-16
申请号：US465461
申请日：1995-06-05
申请人： Takao Akaogi , Masanobu Yoshida , Yasushige Oqawa , Yasushi Kasa , Shouichi Kawamura
发明人： Takao Akaogi , Masanobu Yoshida , Yasushige Oqawa , Yasushi Kasa , Shouichi Kawamura
IPC分类号： G11C16/26 , G11C16/30 , G11C29/04 , G11C7/00
CPC分类号： G11C16/30 , G11C16/26 , G11C29/04 , G06F2201/81
摘要： When a current flows through a selected memory cell transistor at the time of data reading, the gate voltage of an n-channel MOS transistor, which makes up the current flowing through the load, rises. Thus, when a current flows through a selected memory cell transistor at the time of data reading, the current through the load is increased so that the time required for data reading when the current flows through the selected memory cell transistor can be shortened and the data reading can be effected at a high speed.
摘要翻译：当数据读取时电流流经所选择的存储单元晶体管时，构成流过负载的电流的n沟道MOS晶体管的栅极电压升高。因此，当数据读取时电流流经所选择的存储单元晶体管时，通过负载的电流增加，从而可以缩短电流流经所选择的存储单元晶体管时数据读取所需的时间，并且数据读数可以高速进行。

22. 发明授权

US5519652A Nonvolatile semiconductor memory for positively holding stored data 失效
标题翻译：用于积极保存存储数据的非易失性半导体存储器
公开(公告)号：US5519652A
公开(公告)日：1996-05-21
申请号：US158796
申请日：1993-12-01
申请人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
发明人： Sinsuke Kumakura , Yasushige Ogawa , Takao Akaogi , Tetsuya Chida
IPC分类号： G11C17/00 , G11C16/06 , G11C16/26 , G11C16/28 , G11C29/00 , G11C29/06 , G11C29/50 , G11C29/56 , G11C11/34
CPC分类号： G11C29/50016 , G11C16/26 , G11C16/28 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5006
摘要： A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.
摘要翻译：半导体存储器具有多个字线，多个位线，多个存储单元，差分读出放大器和负载晶体管。每个存储单元是形成在字和位线的每个交叉处的MIS晶体管。 MIS晶体管的阈值电压是外部电可控的。差分读出放大器感测存储在位于选定字和位线的交叉点处的选定存储单元中的数据。控制脉冲信号施加到负载晶体管的栅极，以偏置位线。控制脉冲信号的脉冲宽度是从所选存储单元读出数据所必需的最小值。控制脉冲信号控制负载晶体管的切换，以缩短连续施加到与所选存储单元连接的位线的未选择存储单元的漏极的应力电压的周期。

23. 发明授权

US5293344A Write circuit for non-volatile memory device 失效
标题翻译：用于非易失性存储器件的写电路
公开(公告)号：US5293344A
公开(公告)日：1994-03-08
申请号：US656502
申请日：1991-02-19
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C7/00 , G11C11/40
CPC分类号： G11C16/10
摘要： A write circuit for a non-volatile memory device includes a plurality of cell transistors and a bit line select transistor, provided with respect to each bit line, for supplying a source current thereof to one of the cell transistors as a drain current of the cell transistor via a corresponding one of the bit lines. The write circuit includes a dummy cell transistor for detecting a breakdown voltage of the cell transistor in a write mode, and a circuit for varying a gate voltage of the bit line select transistor as a function of the breakdown voltage detected by the dummy cell transistor, thereby to make the gate-source voltage of the bit line select transistor approximately constant and to maintain the drain current of the cell transistor during the write mode approximately constant.
摘要翻译：用于非易失性存储器件的写入电路包括相对于每个位线提供的多个单元晶体管和位线选择晶体管，用于将其源极电流提供给单元晶体管中的一个作为单元的漏极电流晶体管通过相应的一个位线。写入电路包括用于在写入模式下检测单元晶体管的击穿电压的虚拟单元晶体管，以及用于根据由虚设单元晶体管检测的击穿电压来改变位线选择晶体管的栅极电压的电路，从而使位线选择晶体管的栅极 - 源极电压近似恒定，并且在写入模式期间保持单元晶体管的漏极电流大致恒定。

24. 发明授权

US5237530A Frasable non-volatile semiconductor memory device having read/write test function 失效
标题翻译：具有读/写测试功能的可擦除非易失性半导体存储器件
公开(公告)号：US5237530A
公开(公告)日：1993-08-17
申请号：US795147
申请日：1991-11-20
申请人： Nobuaki Takashina , Takao Akaogi , Masanobu Yoshida
发明人： Nobuaki Takashina , Takao Akaogi , Masanobu Yoshida
IPC分类号： G11C17/00 , G11C29/08 , G11C29/34 , G11C29/52
CPC分类号： G11C29/34 , G11C29/08 , G11C29/52
摘要： An erasable non-volatile semiconductor memory device has a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detects the write status of each memory cell by a differential type detection circuit through first and second bit lines connected to the two cell transistors. Further, the erasable non-volatile semiconductor memory device sets all cell transistors constructing a plurality of the memory cells to the erasing status or write status in entirety, and controls the connection of the first and second bit lines for executing the read/write test. Therefore, the erasable non-volatile semiconductor memory device according to the present invention can reduce the erasing process cycles, which requires a long time, falsely read out the "0" data and "1" data without writing actual data into each memory cell to shorten the test time, and thus can supply a low price product.
摘要翻译：可擦除非易失性半导体存储器件具有多个可擦除非易失性存储单元，每个可擦除非易失性存储单元包括两个单元晶体管，其写状态被反相，并且通过差分型检测电路首先检测每个存储单元的写状态，连接到两个单元晶体管的第二位线。此外，可擦除非易失性半导体存储器件将构成多个存储单元的所有单元晶体管全部设置为擦除状态或写入状态，并且控制用于执行读/写测试的第一和第二位线的连接。因此，根据本发明的可擦除非易失性半导体存储器件可以减少擦除处理周期，这需要很长时间，错误地读出“0”数据和“1”数据，而不将实际数据写入每个存储器单元缩短测试时间，从而可以提供低价格的产品。

25. 发明授权

US5197030A Semiconductor memory device having redundant memory cells 失效
标题翻译：具有冗余存储器单元的半导体存储器件
公开(公告)号：US5197030A
公开(公告)日：1993-03-23
申请号：US570057
申请日：1990-08-20
申请人： Takao Akaogi , Mitsuo Higuchi
发明人： Takao Akaogi , Mitsuo Higuchi
IPC分类号： G11C8/18 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842 , G11C8/18
摘要： A semiconductor memory device includes a memory cell array, a data readout circuit, a decoder circuit and an address transition detecting circuit which detects an address transition of an input address signal and which generates an address transition detection pulse. A redundancy circuit determines whether or not the input address signal indicates a defective memory cell and outputs a redundancy signal to the decoder so that the decoder selects one redundant memory cell in place of the specified defective memory cell. A pulse generator generates a pulse signal having a pulse duration time sufficient to reset the memory cell array and the data readout circuit before reading data from the memory cell array in a case where the redundancy circuit outputs the redundancy signal. The pulse duration time of the pulse signal starts from a time when the address transition detecting circuit generates the address transition signal.

26. 发明授权

US08638609B2 Partial local self boosting for NAND 有权
标题翻译： NAND的部分本地自增强
公开(公告)号：US08638609B2
公开(公告)日：2014-01-28
申请号：US12783351
申请日：2010-05-19
申请人： Ya-Fen Lin , Colin Bill , Takao Akaogi , Youseok Suh
发明人： Ya-Fen Lin , Colin Bill , Takao Akaogi , Youseok Suh
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.
摘要翻译：存储器系统被编程为在自增强期间具有最少的程序干扰和减少的结和通道泄漏。在将程序信号施加到所选择的字线之前，预充电偏置信号被施加到与所选字线相邻的字线，并且将通过信号施加到剩余的字线。预充电偏压信号将预充电施加到存储器单元。选择预充电偏压信号以改善与所选字线相邻的字线上的存储器单元的隔离，提高自升压效率并减少电流泄漏以防止或减少程序干扰和/或编程错误，特别是在禁止的存储器所选字线上的单元格。

27. 发明申请

US20120170377A1 LOCAL WORD LINE DRIVER AND FLASH MEMORY ARRAY DEVICE THEREOF 有权
标题翻译：本地字线驱动器及其闪存存储器阵列
公开(公告)号：US20120170377A1
公开(公告)日：2012-07-05
申请号：US12980442
申请日：2010-12-29
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C16/08
CPC分类号： G11C16/08 , G11C8/08
摘要： In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.
摘要翻译：在NOR闪存的本地字线驱动器及其闪速存储器阵列器件中，提供本地字线驱动器用于驱动存储器阵列的扇区中的本地字线，并且本地字线驱动器具有两个晶体管，包括：第一晶体管和第二晶体管，并且第一和第二晶体管是NMOS晶体管，从而实现减少局部字线驱动器上的电路占用的面积和芯片尺寸的效果，并且保存由存储器单元使用的区域。

28. 发明授权

US07791947B2 Non-volatile memory device and methods of using 有权
标题翻译：非易失性存储器件及其使用方法
公开(公告)号：US07791947B2
公开(公告)日：2010-09-07
申请号：US11972312
申请日：2008-01-10
申请人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
发明人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115
摘要： The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.
摘要翻译：本公开调整NAND串的选择栅极的电压阈值。可以读取，擦除和编程NAND串的选择栅极。

29. 发明申请

US20090201724A1 MEMORY DEVICE AND METHOD THEREOF 有权
标题翻译：存储器件及其方法
公开(公告)号：US20090201724A1
公开(公告)日：2009-08-13
申请号：US12030485
申请日：2008-02-13
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/04 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A device and corresponding method of using a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier is disclosed. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent disclosing time can be achieved at a sense node of a sense amplifier.
摘要翻译：公开了一种使用温度依赖偏置发生器产生施加到读出放大器的控制栅极的电压的装置和相应方法。通过将温度依赖偏置信号应用于读出放大器，可以在感测放大器的感测节点处实现基本上温度独立的公开时间。

30. 发明申请

US20090180330A1 NON-VOLATILE MEMORY DEVICE AND METHODS OF USING 有权
标题翻译：非易失性存储器件及其使用方法
公开(公告)号：US20090180330A1
公开(公告)日：2009-07-16
申请号：US11972312
申请日：2008-01-10
申请人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
发明人： Michael A. VanBuskirk , Colin S. Bill , Takao Akaogi
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/0483 , H01L27/115
摘要： The present disclosure adjusts the voltage threshold values of select gates of NAND strings. The select gates of the NAND string can be read, erased, and programmed.
摘要翻译：本公开调整NAND串的选择栅极的电压阈值。可以读取，擦除和编程NAND串的选择栅极。

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