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21. 发明申请

US20050153497A1 Method of forming a FET having ultra-low on-resistance and low gate charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US20050153497A1
公开(公告)日：2005-07-14
申请号：US10997818
申请日：2004-11-24
申请人： Izak Bencuya , Brian Mo , Ashok Challa
发明人： Izak Bencuya , Brian Mo , Ashok Challa
IPC分类号： H01L21/336 , H01L29/08 , H01L29/423 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

22. 发明授权

US06710406B2 Field effect transistor and method of its manufacture 有权
公开(公告)号：US06710406B2
公开(公告)日：2004-03-23
申请号：US10155554
申请日：2002-05-24
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L2978
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

23. 发明授权

US4566172A Method of fabricating a static induction type recessed junction field effect transistor 失效
标题翻译：制造静态感应型凹结场效应晶体管的方法
公开(公告)号：US4566172A
公开(公告)日：1986-01-28
申请号：US583512
申请日：1984-02-24
申请人： Izak Bencuya , Adrian I. Cogan
发明人： Izak Bencuya , Adrian I. Cogan
IPC分类号： H01L21/335 , H01L29/10 , H01L21/425
CPC分类号： H01L29/66416 , H01L29/1066
摘要： Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. The depth of the grooves is increased by etching to remove most of the P-type zone underlying each groove while leaving laterally extending P-type portions. Oxygen is implanted to convert the remainder of the P-type zones underlying the end walls of the grooves to silicon dioxide. Metal layers are deposited in the bottoms of the grooves making contact with the P-type portions. The grooves are filled with filler material and materials are etched away to produce a flat, planar surface with low resistivity N-type silicon of the ridges exposed in the surface and with filler material in the grooves also exposed at the surface. A large area metal contact is applied which extends across the surface and makes ohmic contact to the low resistivity N-type silicon of all the ridges.
摘要翻译：结型场效应晶体管，特别是静态感应晶体管及其制造方法。在低电阻N型硅衬底上生长的高电阻率N型外延层的表面形成低电阻率N型层。低电阻率N型层的表面涂覆有氮化硅，部分氮化硅被去除并且蚀刻硅以形成具有插入的硅脊的平行凹槽。在凹槽中生长二氧化硅，从凹槽的端壁移除，并且在凹槽的端壁处形成P型区域。通过蚀刻来增加凹槽的深度以去除每个凹槽下面的大部分P型区域，同时留下横向延伸的P型部分。植入氧气以将槽的端壁下面的P型区域的其余部分转化为二氧化硅。金属层沉积在与P型部分接触的凹槽的底部。凹槽填充有填充材料，并且材料被蚀刻掉以产生平坦的平坦表面，其表面露出的脊的电阻率低的N型硅，并且槽中的填充材料也暴露在表面。施加大面积金属接触，其延伸穿过表面并与所有脊的低电阻率N型硅欧姆接触。

24. 发明授权

US08710584B2 FET device having ultra-low on-resistance and low gate charge 有权
标题翻译： FET器件具有超低导通电阻和低栅极电荷
公开(公告)号：US08710584B2
公开(公告)日：2014-04-29
申请号：US13344269
申请日：2012-01-05
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate, the substrate being heavily doped and of a first conductivity type, a substrate cap region disposed on the substrate, the substrate cap region being heavily doped and of the first conductivity type and a body region disposed on the substrate cap region, the body region being lightly doped and of a second conductivity type. The MOSFET also includes a trench extending into the body region, a source region of the first conductivity type disposed in the body region and in contact with an upper portion of a sidewall of the trench and an out-diffusion region of the first conductivity type formed such that a spacing between the source region and the out-diffusion region defines a channel region of the MOSFET extending along the sidewall of the trench.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括衬底，衬底被重掺杂并具有第一导电类型，衬底帽区域设置在衬底上，衬底帽区域被重掺杂并且具有第一导电类型以及设置在所述基板盖区域上的主体区域，所述主体区域被轻掺杂并具有第二导电类型。 MOSFET还包括延伸到体区的沟槽，设置在体区中并与沟槽的侧壁的上部接触的第一导电类型的源区和形成的第一导电类型的扩散区使得源极区域和外扩散区域之间的间隔限定沿着沟槽的侧壁延伸的MOSFET的沟道区域。

25. 发明授权

US08476133B2 Method of manufacture and structure for a trench transistor having a heavy body region 有权
标题翻译：具有重体区域的沟槽晶体管的制造方法和结构
公开(公告)号：US08476133B2
公开(公告)日：2013-07-02
申请号：US12685592
申请日：2010-01-11
申请人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
发明人： Brian Sze-Ki Mo , Duc Chau , Steven Sapp , Izak Bencuya , Dean Edward Probst
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
摘要翻译：提供了沟槽场效应晶体管，其包括（a）半导体衬底，（b）在半导体衬底中延伸预定深度的沟槽，（c）位于沟槽相对侧上的一对掺杂源极结（d ）掺杂的重体，其位于与沟槽的源极结的相对侧上的每个源极结附近，重体的最深部分比沟槽的预定深度更深地延伸到所述半导体衬底中，以及（e）掺杂很好地围着沉重的身体下面的沉重的身体。

26. 发明申请

US20120171828A1 Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US20120171828A1
公开(公告)日：2012-07-05
申请号：US13344269
申请日：2012-01-05
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

27. 发明授权

US08101484B2 Method of forming a FET having ultra-low on-resistance and low gate charge 有权
标题翻译：形成具有超低导通电阻和低栅极电荷的FET的方法
公开(公告)号：US08101484B2
公开(公告)日：2012-01-24
申请号：US12821590
申请日：2010-06-23
申请人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
发明人： Izak Bencuya , Brian Sze-Ki Mo , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/42368
摘要： In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
摘要翻译：根据本发明的示例性实施例，提供了第一导电型硅的衬底。形成第一导电型硅的衬底帽区域，使得在衬底帽区域和衬底之间形成结。形成第二导电型硅的体区，使得在体区和衬底帽区之间形成接合部。然后形成至少延伸穿过身体区域的沟槽。然后在身体区域的上部形成第一导电类型的源极区域。作为一个或多个温度循环的结果，第一导电类型的扩散区形成在体区的下部，使得源极区域和外扩散区域之间的间隔限定了场的沟道长度效应晶体管。

28. 发明授权

US5430324A High voltage transistor having edge termination utilizing trench technology 失效
标题翻译：具有利用沟槽技术的边缘终端的高压晶体管
公开(公告)号：US5430324A
公开(公告)日：1995-07-04
申请号：US918996
申请日：1992-07-23
申请人： Izak Bencuya
发明人： Izak Bencuya
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/40 , H01L29/78 , H01L23/58 , H01L29/76 , H01L29/94
CPC分类号： H01L29/0619 , H01L29/404 , H01L29/407 , H01L29/66348 , H01L29/7811 , H01L29/7813
摘要： For a vertical DMOS power transistor or a high voltage bipolar transistor, an edge termination at the perimeter of the die surrounding the active transistor cells includes multiple spaced apart field rings. A trench is located between each adjacent pair of field rings and is insulated either by oxide formed on the sidewalls thereof or by an oxide filling. The insulated trenches allow the field rings to be very closely spaced together. Advantageously the trenches may be formed in the same process steps as are the trenched gate electrodes of the active portion of the transistor. This structure eliminates the necessity for fabricating thick field oxide underlying a conventional field plate termination, and hence allows fabrication of a transistor without the need for a field plate termination, and in which the multiple field rings are suitable for a transistor device having a breakdown voltage in the range of 20 to 150 volts. The trenches advantageously eliminate the process sensitivity of using multi field ring terminations with low resistivity semiconductor material.
摘要翻译：对于垂直DMOS功率晶体管或高压双极晶体管，围绕有源晶体管单元的管芯周边的边缘端接包括多个间隔开的场环。沟槽位于每个相邻的一对场环之间，并且通过在其侧壁上形成的氧化物或通过氧化物填充绝缘。绝缘沟槽允许场环非常紧密地隔开。有利地，沟槽可以以与晶体管的有源部分的沟槽栅电极相同的工艺步骤形成。该结构消除了在常规场板端接下面制造厚场氧化物的必要性，因此允许制造晶体管而不需要场板端接，并且其中多场环适用于具有击穿电压的晶体管器件在20到150伏的范围内。沟槽有利地消除了使用具有低电阻率半导体材料的多场环端接的工艺灵敏度。

29. 发明授权

US4751556A Junction field effect transistor 失效
标题翻译：结场效应晶体管
公开(公告)号：US4751556A
公开(公告)日：1988-06-14
申请号：US65134
申请日：1987-06-24
申请人： Adrian I. Cogan , Izak Bencuya
发明人： Adrian I. Cogan , Izak Bencuya
IPC分类号： H01L29/10 , H01L29/772 , H01L29/80 , H01L29/08
CPC分类号： H01L29/1066 , H01L29/7722
摘要： Junction field effect transistor, specifically a static induction transistor, and method of fabricating. A low resistivity N-type surface layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the surface layer is coated with silicon dioxide and portions of the silicon dioxide layer are removed to expose alternating gate surface areas and source surface areas. P-type conductivity material is diffused into the silicon from the gate surface areas to produce zones of graded concentration. The difference in concentration of N-type conductivity imparting material in the surface layer and in the remainder of the epitaxial layer causes the resulting P-type gate regions to extend laterally toward each other so as to produce narrow channel regions at a depth beyond the surface layer while limiting the lateral extensions of the P-type gate regions adjacent to the surface. The device exhibits both high voltage gain and low gate capacitance.
摘要翻译：结型场效应晶体管，特别是静态感应晶体管及其制造方法。在低电阻N型硅衬底上生长的高电阻率N型外延层的表面形成低电阻率的N型表面层。表面层的表面涂覆有二氧化硅，并且去除部分二氧化硅层以暴露交替的栅表面积和源表面积。 P型导电性材料从栅极表面区域扩散到硅中以产生分级浓度的区域。在表面层和外延层的其余部分中，N型导电性赋予材料的浓度差导致所得到的P型栅极区域相互横向延伸，以便在超过表面的深度处产生窄通道区域同时限制邻近表面的P型栅极区域的横向延伸。该器件表现出高电压增益和低栅极电容。

30. 发明授权

US4611384A Method of making junction field effect transistor of static induction type 失效
标题翻译：制造静态感应型结型场效应晶体管的方法
公开(公告)号：US4611384A
公开(公告)日：1986-09-16
申请号：US729025
申请日：1985-04-30
申请人： Izak Bencuya , Adrian I. Cogan
发明人： Izak Bencuya , Adrian I. Cogan
IPC分类号： H01L21/335 , H01L29/772 , H01L21/265 , H01L21/38 , H01L21/425
CPC分类号： H01L29/66416 , H01L29/7722 , Y10S148/082
摘要： Junction field effect transistor, specifically a static induction transistor, and method of fabricating. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. A layer of silicon nitride is applied and then removed except from the side walls of the grooves. Exposed silicon at the bottoms of the grooves is converted to silicon dioxide to build up layers of silicon dioxide in the grooves. The remaining silicon nitride is removed. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves. N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges. Metal contacts are applied to the gate ridges, the source ridges, and the substrate.
摘要翻译：结型场效应晶体管，特别是静态感应晶体管及其制造方法。在低电阻率硅的衬底上生长高电阻率N型硅的外延层。外延层的表面涂覆有氮化硅，部分氮化硅被去除，并且蚀刻硅以形成具有插入的硅脊的平行凹槽。施加氮化硅层，然后除去沟槽的侧壁之外。在凹槽底部的暴露的硅转化为二氧化硅，以在沟槽中形成二氧化硅层。剩余的氮化硅被去除。 P型导电性材料被离子注入到交替（栅极）脊中并且扩散以形成在相邻沟槽中的二氧化硅的横向下方延伸的栅极区域。 N型导电性材料被离子注入在中间（源极）的顶部。将金属触点施加到栅极脊，源极和基板。

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