专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07075824B2 NAND flash memory device 有权
标题翻译： NAND闪存设备
公开(公告)号：US07075824B2
公开(公告)日：2006-07-11
申请号：US11016286
申请日：2004-12-17
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115 , H01L29/42324
摘要： Disclosed is a NAND flash memory device which includes butting taps that are formed in such a manner that a poly layer and a silicide layer are connected to given points at the ends of a DSL and the SSL of a NAND flash memory device through a metal contact. The butting taps reduces the resistance of the DSL and the SSL and, consequently, reduce the loading time of the DSL and the SSL.
摘要翻译：公开了一种NAND闪速存储器件，其包括对接抽头，其以多层和硅化物层通过金属接触连接到DSL的端部处的给定点和NAND快闪存储器件的SSL的方式形成。对接抽头降低了DSL和SSL的阻力，从而减少了DSL和SSL的加载时间。

22. 发明授权

US07009260B2 Well structure in high voltage device 失效
标题翻译：高压器件结构良好
公开(公告)号：US07009260B2
公开(公告)日：2006-03-07
申请号：US10730299
申请日：2003-12-08
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/0619 , H01L27/115 , H01L29/0615
摘要： A well structure in a high voltage device comprises a first well formed in a substrate, the first well having an opposite conductive type from the substrate; a second well isolated from the first well, the second well having the same conductive type as the substrate; a field stop implant region formed between the first well and the second well and spaced apart from each of the first well and the second well by a given distance, the field stop implant region having the same conductive type as the substrate; and a pick-up region overlapped on the field stop implant region, the pick-up region having the same conductive type as the field stop implant region.
摘要翻译：高压器件中的阱结构包括形成在衬底中的第一阱，第一阱具有与衬底相反的导电类型; 与第一阱隔离的第二阱，第二阱具有与衬底相同的导电类型; 形成在所述第一阱和所述第二阱之间并且与所述第一阱和所述第二阱中的每一个间隔开给定距离的场停止注入区域，所述场停止注入区域具有与所述衬底相同的导电类型; 并且拾取区域与场停止注入区域重叠，拾取区域具有与场停止注入区域相同的导电类型。

23. 发明授权

US08298961B2 Patterns of semiconductor device and method of forming the same 有权
标题翻译：半导体器件的形态及其形成方法
公开(公告)号：US08298961B2
公开(公告)日：2012-10-30
申请号：US12650498
申请日：2009-12-30
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L21/475
CPC分类号： H01L21/0338 , H01L21/0337
摘要： A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns.
摘要翻译：一种形成半导体器件的图形的方法包括提供一种半导体衬底，该半导体衬底包括将要形成第一图案的第一区域和要形成第二图案的第二区域，每个第二图案的宽度比第一图案宽在所述半导体衬底上形成蚀刻目标层，在所述第一和第二区域的所述蚀刻目标层上形成第一蚀刻图案，在所述第一蚀刻图案的每个的两个侧壁上形成第二蚀刻图案，其中形成在所述第一蚀刻图案中的所述第二蚀刻图案第二区域具有比在第一区域中形成的第二蚀刻图案宽的宽度，去除第一蚀刻图案，在第二区域的蚀刻目标层上形成第三蚀刻图案，第二蚀刻图案与第二图案重叠部分，以及蚀刻使用第三蚀刻图案和第二蚀刻图案作为蚀刻掩模的蚀刻目标层，以形成第一和第二图案。

24. 发明授权

US08252660B2 Flash memory device and method of manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US08252660B2
公开(公告)日：2012-08-28
申请号：US12649572
申请日：2009-12-30
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L21/76
CPC分类号： H01L27/11519 , H01L21/76229 , H01L27/11521 , H01L27/11524
摘要： Disclosed herein are flash memory devices and methods of making the same. According to one embodiment, a flash memory device includes first trenches formed in a semiconductor substrate and arranged in parallel, second trenches discontinuously formed in the semiconductor substrate and arranged between the first trenches, first isolation structures respectively formed within the first trenches, second isolation structures respectively formed within the second trenches, and active regions defined by the first isolation structures and the second isolation structures.
摘要翻译：本文公开了闪存器件及其制造方法。根据一个实施例，闪速存储器件包括形成在半导体衬底中并且平行布置的第一沟槽，第二沟槽不连续地形成在半导体衬底中并且布置在第一沟槽之间，分别形成在第一沟槽内的第一隔离结构，第二隔离结构分别形成在第二沟槽内，以及由第一隔离结构和第二隔离结构限定的有源区。

25. 发明授权

US07643067B2 Rectification system and method of stereo image in real-time 有权
标题翻译：立体图像的整流系统和方法实时
公开(公告)号：US07643067B2
公开(公告)日：2010-01-05
申请号：US11677324
申请日：2007-02-21
申请人： Jae Wook Jeon , Seung Hun Jin , Jung Uk Cho , Sung Kee Park , Munsang Kim , Kyoung Mu Lee , Jong Eun Byun
发明人： Jae Wook Jeon , Seung Hun Jin , Jung Uk Cho , Sung Kee Park , Munsang Kim , Kyoung Mu Lee , Jong Eun Byun
IPC分类号： H04N5/225 , H04N13/00 , H04N5/228 , H04N9/04 , G06K9/32
CPC分类号： G06K9/209 , G06K9/03 , G06T3/0075 , G06T3/4007 , G06T2200/28 , G06T2207/10021 , H04N13/239 , H04N13/246
摘要： Disclosed is a system and a method for rectifying stereo images, which are acquired by two cameras, in real-time by using a calibration matrix resulting from camera calibration. The system includes a coordinate generation module; a rectification coordinate generation module; a bilinear interpolation value generation module; a rectification coordinate memory; a bilinear interpolation memory; an image buffer; an rectification module; and a control module. A structure of a hardware system capable of real-time stereo rectification is provided, and the operation results have been verified by implementing a hardware device. The real-time stereo rectification system makes it possible to acquire rectified images in real-time without using a separate computer system or a software program.
摘要翻译：公开了通过使用由相机校准产生的校准矩阵来实时校正由两个摄像机获取的立体图像的系统和方法。该系统包括坐标生成模块; 整流坐标生成模块; 双线性内插值生成模块; 整流坐标记忆; 双线性插值记忆; 图像缓冲区整改模块; 和控制模块。提供能够实时立体声整流的硬件系统的结构，并且通过实施硬件设备来验证操作结果。实时立体声整流系统使得可以实时获取整流图像而不使用单独的计算机系统或软件程序。

26. 发明申请

US20060258129A1 Isolation film in semiconductor device and method of forming the same 失效
标题翻译：半导体器件中的隔离膜及其形成方法
公开(公告)号：US20060258129A1
公开(公告)日：2006-11-16
申请号：US11155747
申请日：2005-06-20
申请人： Sung Kee Park
发明人： Sung Kee Park
IPC分类号： H01L21/425 , H01L21/8238
CPC分类号： H01L21/76224 , H01L27/11526 , H01L27/11531
摘要： The present invention relates to an isolation film in a semiconductor device and method of forming the same. An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the isolation film is thicker than an isolation film of the cell region so that a parasitic transistor is not generated and a leakage current can be prevented.
摘要翻译：本发明涉及一种半导体器件中的隔离膜及其制造方法。隔离膜形成在周边区域的掺杂区域中，其中掺杂区域与单元区域的深阱区域隔离，并且隔离膜比单元区域的隔离膜厚，使得寄生晶体管为不产生并且可以防止泄漏电流。

27. 发明授权

US07099198B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US07099198B2
公开(公告)日：2006-08-29
申请号：US10968687
申请日：2004-10-19
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.
摘要翻译：闪速存储器中的行解码器包括用于选择性地将字线耦合到第一电压端子的第一开关和用于选择性地将字线耦合到第二电压端子的第二开关。行解码器还包括用于选择性地将字线耦合到第三电压端子的第三开关。

28. 发明授权

US06819597B2 Row decoder in flash memory and erase method of flash memory cell using the same 有权
标题翻译：闪存中的行解码器和闪存单元的擦除方法使用相同
公开(公告)号：US06819597B2
公开(公告)日：2004-11-16
申请号：US10614229
申请日：2003-07-07
申请人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
发明人： Ki Seog Kim , Keun Woo Lee , Sung Kee Park , Yoo Nam Jeon
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： Disclosed are a row decoder in a flash memory and erasing method in a flash memory cell using the same. The row decoder comprises a PMOS transistor having a gate electrode for receiving a first input signal as an input and connected between a first power supply terminal and a first node, a first NMOS transistor having a gate electrode for receiving the first input signal as an input and connected between the first node and a second node, a second NMOS transistor having a gate electrode for receiving the second input signal as an input and connected between the second node and a ground terminal, and a switching means having a gate electrode for receiving the third input signal as an input and connected between the second node and a second power supply terminal, wherein the first node is connected to word lines.
摘要翻译：本发明公开了一种闪速存储器中的行解码器和使用其的擦除方法。行解码器包括具有用于接收第一输入信号作为输入并连接在第一电源端子和第一节点之间的栅电极的PMOS晶体管，具有用于接收第一输入信号作为输入的栅电极的第一NMOS晶体管并连接在第一节点和第二节点之间的第二NMOS晶体管，具有用于接收第二输入信号作为输入并连接在第二节点和接地端子之间的栅电极的第二NMOS晶体管，以及具有栅电极的开关装置，第三输入信号作为输入并连接在第二节点和第二电源端子之间，其中第一节点连接到字线。

29. 发明授权

US06743676B2 Method of forming a floating gate in a flash memory device 失效
标题翻译：在闪速存储器件中形成浮动栅极的方法
公开(公告)号：US06743676B2
公开(公告)日：2004-06-01
申请号：US10286980
申请日：2002-11-04
申请人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
发明人： Sung Kee Park , Ki Seog Kim , Keun Woo Lee , Keon Soo Shim
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.
摘要翻译：本发明涉及一种在闪速存储器件中形成浮动栅极的方法。在形成器件隔离膜时，限定用于浮置栅极的下多晶硅层的空间，通过随后的良好牺牲氧化过程和阱氧化过程在沟槽的内表面上形成鸟嘴，以及上部多晶硅层形成浮栅，从而形成浮栅的空间。因此，与现有步进法相比，本发明可以降低成本，因为与自对准浮动模式相比，不需要使用化学机械抛光工艺（CMP）的平坦化处理，因此与现有的步进方法和工艺成本相比不需要掩模处理。

30. 发明授权

US06316313B1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US06316313B1
公开(公告)日：2001-11-13
申请号：US09717002
申请日：2000-11-22
申请人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
发明人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
IPC分类号： H01L218247
CPC分类号： H01L27/112
摘要： There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.
摘要翻译：公开了一种制造闪速存储器件的方法。为了解决现有的闪速存储器件的情况下阱电阻和寄生电容大的问题以及器件的擦除速度较慢的问题，本发明通过使用金属形成扇区单元的阱区硅化物层并且通过使用合金层来限定晶胞。因此，它可以降低阱电阻和寄生电容。此外，它可以提高装置的操作速度，并且可以通过允许单元单元的擦除操作来降低制造成本。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式