专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06600690B1 Sense amplifier for a memory having at least two distinct resistance states 失效
标题翻译：用于具有至少两个不同电阻状态的存储器的感测放大器
公开(公告)号：US06600690B1
公开(公告)日：2003-07-29
申请号：US10184784
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni , Chitra K. Subramanian
发明人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni , Chitra K. Subramanian
IPC分类号： G11C702
CPC分类号： G11C11/14 , G11C7/067 , G11C7/14 , G11C2207/063
摘要： In a memory, a sensing system detects bit states using one data and two reference inputs, to sense a difference in conductance of a selected memory bit cell and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell in the high conductance state and a memory cell in the low conductance state. The data input is coupled to the selected memory bit cell. The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages amplifies the sense amplifier output without injecting parasitic errors.
摘要翻译：在存储器中，感测系统使用一个数据和两个参考输入来检测位状态，以感测所选存储位单元的电导差和中点参考电导。产生参考电导作为高电导状态的存储单元的平均电导和低电导状态的存储单元。数据输入耦合到所选择的存储器位单元。两个参考输入分别以高和低电导存储器状态耦合到存储器单元。读出放大器使用电流偏置或电压偏置来在位单元之间的预定电压范围内施加感测电压。耦合到读出放大器的互补输出的电容由电路设计来平衡。在一种形式中，两个参考输入是内部连接的。几个增益级之一放大读出放大器输出，而不会注入寄生错误。

22. 发明授权

US06580298B1 Three input sense amplifier and method of operation 有权
标题翻译：三路输入读出放大器及其操作方法
公开(公告)号：US06580298B1
公开(公告)日：2003-06-17
申请号：US10186363
申请日：2002-06-28
申请人： Chitra K. Subramanian , Bradley J. Garni , Joseph J. Nahas , Thomas W. Andre
发明人： Chitra K. Subramanian , Bradley J. Garni , Joseph J. Nahas , Thomas W. Andre
IPC分类号： G11C706
CPC分类号： G11C7/062 , G11C11/16 , G11C2207/063
摘要： A sense amplifier having three inputs determines the state of a memory bit cell by converting a bit input voltage, a high reference voltage, and a low reference voltage to respective current values. Current differences are formed between a bit current and a high reference current, and between a low reference current and a bit current. Current mirrors (154, 158 and 170, 166) and loads (160 and 168) are used in conjunction with current steering circuitry (150, 140, 142 and 162) to form the difference of the bit current and the high reference current and also form the difference of the low reference current and the bit current. Additionally, the sense amplifier drives differential outputs (OUT and OUT13B) to reflect the difference between the two current differential quantities.
摘要翻译：具有三个输入的读出放大器通过将位输入电压，高参考电压和低参考电压转换为相应的电流值来确定存储器位单元的状态。在位电流和高参考电流之间以及低参考电流和位电流之间形成电流差。电流镜（154,158和170,166）和负载（160和168）与电流控制电路（150,140,142和162）结合使用以形成比特电流和高参考电流的差异形成低参考电流和位电流的差异。此外，读出放大器驱动差分输出（OUT和OUT13B）以反映两个电流差分量之间的差异。

23. 发明授权

US5958508A Process for forming a semiconductor device 失效
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US5958508A
公开(公告)日：1999-09-28
申请号：US828635
申请日：1997-03-31
申请人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
发明人： Olubunmi Olufemi Adetutu , Dean J. Denning , James D. Hayden , Chitra K. Subramanian , Arkalgud R. Sitaram
IPC分类号： H01L29/43 , C23C16/44 , C23C16/455 , H01L21/02 , H01L21/205 , H01L21/28 , H01L21/768 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , C23C16/00 , H01L21/285
CPC分类号： C23C16/45523 , H01L21/76895 , H01L28/60
摘要： A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher silicon content near the layer's lower and upper surfaces. At the midpoint, the layer is close to stoichiometric tungsten silicide. In another embodiment, a metal-semiconductor-nitrogen layer is formed having nitrogen nearer the lower surface and essentially no nitrogen near the upper surface. The layer (26) can be formed using chemical vapor deposition or sputtering.
摘要翻译：金属半导体层（26）形成在绝缘层（20）上，使得金属半导体层（26）被分级以在整个层中具有不同量的半导体和金属。在一个实施例中，金属半导体层（26）在层的下表面和上表面附近具有相对较高的硅含量。在中点处，该层接近化学计量的硅化钨。在另一个实施方案中，形成具有更靠近下表面的氮并且在上表面附近基本上不含氮的金属 - 半导体 - 氮层。层（26）可以使用化学气相沉积或溅射形成。

24. 发明授权

US5824579A Method of forming shared contact structure 失效
标题翻译：形成共同接触结构的方法
公开(公告)号：US5824579A
公开(公告)日：1998-10-20
申请号：US632207
申请日：1996-04-15
申请人： Chitra K. Subramanian , James D. Hayden
发明人： Chitra K. Subramanian , James D. Hayden
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , Y10S148/02
摘要： A shared contact structure (30) is formed to electrically connect three coupling layers (59,60,46) to each other and to an active region (33) in a semiconductor substrate (31). A first coupling layer (59) and a second coupling layer (60) are formed such that they are physically isolated from each other. The second coupling layer (60) is formed such that it is in physical contact with the active region (33). A contact opening (45) is formed, which exposes a portion of coupling layers (59, 60). The third coupling layer (46) is then formed so that it is in electrical contact with the second coupling layer (60) and the first coupling layer (59).
摘要翻译：形成共享接触结构（30）以将三个耦合层（59,60,46）彼此电连接到半导体衬底（31）中的有源区（33）。形成第一耦合层（59）和第二耦合层（60），使得它们彼此物理隔离。第二耦合层（60）形成为与活性区域（33）物理接触。形成接触开口（45），其露出一部分耦合层（59,60）。然后形成第三耦合层（46），使得其与第二耦合层（60）和第一耦合层（59）电接触。

25. 发明申请

US20130301346A1 SELF REFERENCING SENSE AMPLIFIER FOR SPIN TORQUE MRAM 有权
标题翻译：自适应感应放大器用于旋转扭矩MRAM
公开(公告)号：US20130301346A1
公开(公告)日：2013-11-14
申请号：US13872993
申请日：2013-04-29
申请人： Chitra K. Subramanian , Syed M. Alam
发明人： Chitra K. Subramanian , Syed M. Alam
IPC分类号： G11C11/16
CPC分类号： G11C11/1673
摘要： Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.
摘要翻译：电路和方法通过使用其在一个状态下的施加电压与相对恒定电阻的电阻变化的特性来提供电阻式存储器单元的自参考感测，而不管其相反状态下的施加电压如何。基于具有均衡电阻的初始偏置状态，使用模拟位线和位线之间的第二偏置状态下的电流比较来确定存储器单元的状态，因为电流的显着差异意味着存储单元状态具有显着的电阻系数。施加到模拟位线的偏移电流可选地可以用于提供对称性和更大的感测余量。

26. 发明授权

US07543211B2 Toggle memory burst 有权
标题翻译：切换内存突发
公开(公告)号：US07543211B2
公开(公告)日：2009-06-02
申请号：US11047544
申请日：2005-01-31
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian
IPC分类号： H03M13/00
CPC分类号： G11C7/22 , G11C11/16 , G11C2207/2263
摘要： A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.
摘要翻译：一种用于触发存储器的控制器，其通过读取触发存储器中的一组位来执行突发写入，并将该脉冲串的每个接收到的数据字与该组的一部分进行比较，以确定哪个单元切换以输入突发写入的数据切换存储器。在一个示例中，触发存储器包括具有使用多个自由磁性层的单元的磁阻随机存取存储器（MRAM），当沿两个方向受到一系列磁脉冲时，该状态在状态之间切换。因为对脉冲串的一组数据执行一次读取，所以执行突发写入所需的时间减少。

27. 发明授权

US06744663B2 Circuit and method for reading a toggle memory cell 有权
公开(公告)号：US06744663B2
公开(公告)日：2004-06-01
申请号：US10184811
申请日：2002-06-28
申请人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
发明人： Brad J. Garni , Thomas W. Andre , Joseph J. Nahas , Chitra K. Subramanian
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (1300, 1500). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (1300, 1500). The first signal is compared to the second signal to determine the state of the MRAM cell.

28. 发明授权

US06693824B2 Circuit and method of writing a toggle memory 失效
标题翻译：写入切换存储器的电路和方法
公开(公告)号：US06693824B2
公开(公告)日：2004-02-17
申请号：US10186141
申请日：2002-06-28
申请人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
发明人： Joseph J. Nahas , Thomas W. Andre , Chitra K. Subramanian , Brad J. Garni
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.
摘要翻译：磁阻随机存取存储器以触发方式操作，使得其写入时其逻辑状态从其当前状态翻转到备用状态。这提供了更一致和可靠的编程，因为在切换操作期间的磁过渡能量状态是稳定的。然而，在写入情况下，这意味着在单元被翻转之前，单元格的状态必须被读取并与单元格的期望状态进行比较。如果单元已经处于所需的逻辑状态，则不应写入。写入前的读取时间损失通过在读取时开始写入处理而减少，然后在单元格已经处于所需状态时中止写入步骤。写入实际上可以在单元格上开始并被中止，而不会不利地影响单元的状态。

29. 发明授权

US06667899B1 Magnetic memory and method of bi-directional write current programming 失效
标题翻译：磁存储器和双向写入电流编程方法
公开(公告)号：US06667899B1
公开(公告)日：2003-12-23
申请号：US10401195
申请日：2003-03-27
申请人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
发明人： Chitra K. Subramanian , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A magnetic memory (400) is programmed by selectively conducting current in opposite directions in both word and bit lines to reduce electromigration effects in word lines and bit lines. Various criteria, such as a data value being programmed and a previous current direction are used to determine the direction of the write currents used in the word and bit lines during programming.
摘要翻译：通过在字线和位线中的相反方向选择性地导通电流来编程磁存储器（400），以减少字线和位线中的电迁移效应。使用诸如正在编程的数据值和先前的当前方向的各种标准来确定在编程期间在字和位线中使用的写入电流的方向。

30. 发明授权

US5668021A Process for fabricating a semiconductor device having a segmented channel region 失效
标题翻译：具有分段通道区域的半导体器件的制造方法
公开(公告)号：US5668021A
公开(公告)日：1997-09-16
申请号：US658972
申请日：1996-06-04
申请人： Chitra K. Subramanian , James D. Hayden
发明人： Chitra K. Subramanian , James D. Hayden
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/266
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/42376 , H01L29/66553 , H01L29/66537 , H01L29/7833
摘要： A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).
摘要翻译：制造具有分段沟道区（48）的MOS器件（44）的工艺包括制造复合MOS栅电极（46）。通过在第一多晶硅层（14）上形成开口（18）和绝缘层（16）来形成分段通道区域（48）和MOS栅电极（46）。形成在半导体衬底（10）中的MOS栅电极（46）和掩埋结区（24）的横向范围由第一侧壁间隔件（22）和与第一侧壁间隔件（32）相邻形成的第二侧壁间隔件侧壁间隔件（22）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式