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21. 发明授权

US06664128B2 Bump fabrication process 有权
标题翻译：凸起制造工艺
公开(公告)号：US06664128B2
公开(公告)日：2003-12-16
申请号：US10248716
申请日：2003-02-12
申请人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
发明人： Ho-Ming Tong , Chun-Chi Lee , Jen-Kuang Fang , Min-Lung Huang , Jau-Shoung Chen , Ching-Huei Su , Chao-Fu Weng , Yu-Chen Chou , Tsung-Hua Wu , Su Tao
IPC分类号： H01L2144
CPC分类号： C25F3/02 , C23F1/26 , H01L21/32134 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/1147 , H01L2224/131 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/3473 , H05K2203/054 , H01L2224/13099 , H01L2924/00014
摘要： The present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps in sequence over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant mainly comprises sulfuric acid and de-ionized water. The etchant can etch the nickel-vanadium layer of the UBM layer without damaging the bumps.
摘要翻译：本发明提供一种凸块制造工艺。在衬底上顺序地形成凹凸不平的冶金（UBM）层和凸块之后，用蚀刻剂蚀刻未被凸块覆盖的凸块下金属层。蚀刻剂主要包括硫酸和去离子水。蚀刻剂可以蚀刻UBM层的镍钒层，而不会损坏凸块。

22. 发明授权

US06461897B2 Multichip module having a stacked chip arrangement 有权
标题翻译：具有堆叠芯片布置的多芯片模块
公开(公告)号：US06461897B2
公开(公告)日：2002-10-08
申请号：US09854486
申请日：2001-05-15
申请人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
发明人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01087 , H01L2924/00014 , H01L2924/00012
摘要： A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
摘要翻译：多芯片模块包括至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。半导体芯片以堆叠方式安装到基板上，其中上芯片以下述方式附接到下芯片的有源表面，使得上芯片的任何部分不影响下芯片的每个键合焊盘的垂直视线芯片以允许其引线接合。因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

23. 发明授权

US06359340B1 Multichip module having a stacked chip arrangement 有权
标题翻译：具有堆叠芯片布置的多芯片模块
公开(公告)号：US06359340B1
公开(公告)日：2002-03-19
申请号：US09628676
申请日：2000-07-28
申请人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao , Jian Wen Chen
发明人： Chun Hung Lin , Kuang-Hui Chen , Shyh-Wei Wang , Su Tao , Jian Wen Chen
IPC分类号： H05K706
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2924/01087 , H01L2924/10253 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A multichip module has at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. In some embodiments, the semiconductor chips may have a plurality of bonding pads along only two mutually perpendicular side edges thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
摘要翻译：多芯片模块具有至少两个半导体芯片，其中每个半导体芯片具有在其有效表面上形成并沿着其一个侧边缘设置的一排焊盘。在一些实施例中，半导体芯片可以具有仅沿着其两个相互垂直的侧边缘的多个接合焊盘。半导体芯片以堆叠方式安装到基板上，其中上部芯片以下述方式附接到下部芯片的有源表面，即，上部芯片的任何部分不影响下部芯片的每个焊盘的垂直视线芯片以允许其引线接合。因此，在将芯片堆叠在基板上之后，所有半导体芯片都可以同时引线接合。这允许所有芯片的线接合在一个步骤中完成，以便增加UPH（每小时单位），从而降低制造MCM的成本。

24. 发明授权

US06348729B1 Semiconductor chip package and manufacturing method thereof 有权
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US06348729B1
公开(公告)日：2002-02-19
申请号：US09390695
申请日：1999-09-07
申请人： Sai Man Li , Chun Hung Lin , Shin Hua Chao , Su Tao
发明人： Sai Man Li , Chun Hung Lin , Shin Hua Chao , Su Tao
IPC分类号： H01L2352
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01077 , H01L2924/01079 , H01L2924/181 , H01L2924/18165 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.
摘要翻译：半导体芯片封装通常包括引线框架，半导体管芯和塑料封装体。引线框架包括多个引线和窗垫。窗垫通过连接杆连接到引线框架。多个引线的内端限定中心区域。窗垫设置在中心区域中并且具有限定在其中的开口。半导体管芯设置在窗垫的开口中，并且在其活性表面上形成有多个接合焊盘。引线的内端通过多根接合线与半导体管芯上的焊盘相互连接。引线框架，半导体管芯和接合线被封装在塑料封装主体中，其中引线框架的下表面和半导体管芯的后表面通过塑料封装主体露出。

25. 发明授权

US06300166B1 Method for packaging a BGA and the structure of a substrate for use with the method 有权
标题翻译：用于包装BGA的方法和用于该方法的基板的结构
公开(公告)号：US06300166B1
公开(公告)日：2001-10-09
申请号：US09385921
申请日：1999-08-30
申请人： Su Tao , Yu-Ching Tsai , Meng-Hui Lin , Chin-Ming Chung
发明人： Su Tao , Yu-Ching Tsai , Meng-Hui Lin , Chin-Ming Chung
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/451 , H01L2224/4824 , H01L2224/73215 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A method for packaging a BGA and the structure of the BGA for using the method are disclosed. The structure of the substrate of the BGA includes multiple pairs of aligned slots (11, 12) defined along the X-axis thereof, and a passage (13) corresponding to and perpendicular to one pair of aligned slots (11, 12). While using the method to package the substrate, one side of the substrate will be entirely covered by a first protective layer to protect the chips and the other side of the substrate will form multiple lines of a second protective layers to protect the bonding wires.
摘要翻译：公开了一种用于封装BGA的方法和使用该方法的BGA的结构。 BGA的衬底的结构包括沿着其X轴限定的多对对准的缝隙（11,12），和对应于并垂直于一对对齐的槽（11,12）的通道（13）。当使用该方法封装衬底时，衬底的一侧将被第一保护层完全覆盖以保护芯片，并且衬底的另一侧将形成多条第二保护层以保护接合线。

26. 发明授权

US06172318B2 Base for wire bond checking 有权
标题翻译：焊丝检查基准
公开(公告)号：US06172318B2
公开(公告)日：2001-01-09
申请号：US09379313
申请日：1999-08-23
申请人： Chin-Chen Wang , Yao-Hsin Feng , Su Tao
发明人： Chin-Chen Wang , Yao-Hsin Feng , Su Tao
IPC分类号： H01L2160
CPC分类号： G01R31/2853 , H01L22/12 , H01L2224/48091 , H01L2224/48227 , H01L2924/01079 , H01L2924/00014
摘要： A base mainly includes a heating plate and a probe. The probe is attached to the surface of a heating plate which serves to place a substrate having an ball pad on a lower surface facing the probe of the heating plate. The probe contacts the ball pad of the lower surface of the substrate to form a closed loop for wire bond checking while the substrate is placed on the heating plate. When processing the wire bond, the wire connecting the chip and the ball pad of the substrate and the probe connecting to the wire bond checking system form a loop. Then a current is sent to the substrate from the wire bond checking system to check for wire lift bond or missed wire. When the wire bond checking system finds an occurrence of lift bond or missing wire, the wire bonding process stops immediately to avoid unnecessary wire bonding.
摘要翻译：基座主要包括加热板和探头。探针附着在加热板的表面上，该加热板用于将具有球垫的基底放置在面对加热板的探针的下表面上。当衬底放置在加热板上时，探针接触衬底的下表面的球垫以形成用于焊线检查的闭环。在处理引线接合时，连接芯片和基板的球垫的导线和连接到引线键合检查系统的探针形成一个回路。然后从电线键合检查系统将电流发送到基板，以检查电线接合或漏线。当线焊检查系统发现升降接合或缺失线时，引线接合过程立即停止，以避免不必要的引线接合。

27. 发明授权

US6118176A Stacked chip assembly utilizing a lead frame 有权
标题翻译：使用引线框架的堆叠式芯片组件
公开(公告)号：US6118176A
公开(公告)日：2000-09-12
申请号：US298848
申请日：1999-04-26
申请人： Su Tao , Kuang-Lin Lo , Kuang-Chun Chou , Shih-Chih Chen
发明人： Su Tao , Kuang-Lin Lo , Kuang-Chun Chou , Shih-Chih Chen
IPC分类号： H01L23/495
CPC分类号： H01L24/49 , H01L23/4951 , H01L23/49575 , H01L24/32 , H01L2224/32014 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48992 , H01L2224/4911 , H01L2224/73215 , H01L2224/73265 , H01L2224/8592 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01039 , H01L2924/01082 , H01L2924/07802 , H01L2924/12042 , H01L2924/181 , H01L2924/19107
摘要： A stacked chip assembly generally includes a first chip, a second chip and a lead frame. The lower surface of the first chip is pasted onto the lower surface of the second chip by an adhesive film so as to form a stacked chip body. The stacked chip body is disposed on the lead frame. Bonding pads of the upper surface of the first chip are interconnected to the upper surface of the inner leads of the lead frame by bonding wires. Bonding pads of the upper surface of the second chip are interconnected to the lower surface of the inner leads of the lead frame by bonding wires. Therefore, the first chip and the second chip are simultaneously interconnected to an external circuit devices through the lead frame.
摘要翻译：堆叠式芯片组件通常包括第一芯片，第二芯片和引线框架。第一芯片的下表面通过粘合剂膜粘贴到第二芯片的下表面上，以形成堆叠芯片体。堆叠的芯片体设置在引线框架上。第一芯片的上表面的接合焊盘通过接合线互连到引线框架的内引线的上表面。第二芯片的上表面的接合焊盘通过接合线互连到引线框架的内引线的下表面。因此，第一芯片和第二芯片通过引线框架同时与外部电路器件互连。

28. 发明申请

US20070087478A1 Semiconductor chip package and method for manufacturing the same 有权
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US20070087478A1
公开(公告)日：2007-04-19
申请号：US11612393
申请日：2006-12-18
申请人： Su Tao , Shih Lee
发明人： Su Tao , Shih Lee
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L23/36 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/07811 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor chip package mainly comprises an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The present invention is characterized in that the peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate. The present invention further provides a method for manufacturing the semiconductor chip package.
摘要翻译：半导体芯片封装主要包括互连衬底，中心衬底，外围衬底和夹在互连衬底和中心衬底之间的半导体芯片。互连基板具有用于接收半导体芯片的凹腔。本发明的特征在于，外围基板与中央基板分离，从而减小由半导体芯片封装的CTE失配引起的应力。此外，中心基板和周边基板都与机械地和电连接到互连基板，使得半导体芯片通过中心基板和互连基板电连接到外围基板。本发明还提供一种半导体芯片封装的制造方法。

29. 发明授权

US07168352B2 Process for sawing substrate strip 有权
标题翻译：锯切基板条的工艺
公开(公告)号：US07168352B2
公开(公告)日：2007-01-30
申请号：US09394918
申请日：1999-09-13
申请人： Jau-Yuen Su , Tao-Yu Chen , Su Tao
发明人： Jau-Yuen Su , Tao-Yu Chen , Su Tao
IPC分类号： B26D1/00
CPC分类号： H01L21/67092 , B23D59/002 , Y10T83/04 , Y10T83/0495 , Y10T83/05 , Y10T83/0548 , Y10T83/0572 , Y10T83/531
摘要： A process for sawing a substrate strip marks corresponding to substrate areas of substrate strips which are arranged side-by-side on a plate. A saw machine is mechanically moved to the substrate areas and positioned by the alignment marks of corresponding substrate areas for cutting the substrate areas of the substrate strips in the first phase. Then the saw machine is further mechanically moved to the substrate areas again and is positioned by the alignment marks of corresponding substrate areas again for cutting the substrate areas of the substrate strips in the second phase. Therefore, an error in any of the substrate areas in the first phase and second phase will not accumulate to the subsequent substrate areas in the substrate strip.
摘要翻译：用于锯切对应于在板上并排布置的衬底条的衬底区域的衬底条的标记的方法。锯床机械地移动到基板区域并且由对应的基板区域的对准标记定位，以便在第一阶段中切割基板条的基板区域。然后再次将锯床机械地移动到基板区域，并再次通过对应基板区域的对准标记定位，以在第二阶段中切割基板条带的基板区域。因此，第一相和第二相中的任何一个衬底区域中的误差将不会累积到衬底条中的随后的衬底区域。

30. 发明申请

US20060183313A1 Semiconductor package and method for manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20060183313A1
公开(公告)日：2006-08-17
申请号：US11398723
申请日：2006-04-06
申请人： Su Tao
发明人： Su Tao
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05548 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2224/05124
摘要： A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.
摘要翻译：半导体封装包括半导体芯片，盖，多个迹线，柔性层，多个导电浆料和多个焊盘。半导体芯片具有有源表面，背面和设置在有源表面上的多个接合焊盘。盖子覆盖半导体芯片的有源表面。迹线设置在盖和半导体芯片的有源表面之间，并且电连接到接合焊盘。柔性层覆盖用于隔离迹线的半导体芯片的背面。导电膏与导线电连接，焊盘与导电膏电连接。

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