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21. 发明授权

US07521376B2 Method of forming a semiconductor structure using a non-oxygen chalcogen passivation treatment 失效
标题翻译：使用非氧硫属元素钝化处理形成半导体结构的方法
公开(公告)号：US07521376B2
公开(公告)日：2009-04-21
申请号：US11259165
申请日：2005-10-26
申请人： Martin M. Frank , Steven J. Koester , John A. Ott , Huiling Shang
发明人： Martin M. Frank , Steven J. Koester , John A. Ott , Huiling Shang
IPC分类号： H01L21/469
CPC分类号： H01L21/02052 , H01L21/02046 , H01L21/02175 , H01L21/0228 , H01L21/28255 , H01L21/306 , H01L21/31604 , H01L29/513 , H01L29/66181
摘要： A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.
摘要翻译：提供了可以获得诸如FET和MOS电容器的Ge基半导体器件的方法和结构。具体地说，本发明提供了一种形成半导体器件的方法，该半导体器件包括一个包含电介质层和导电材料的叠层，该叠层位于其表面为非氧硫属元素的含Ge材料（层或晶片）之上和/或之内丰富。通过提供非氧贫硫族元素界面，抑制了电介质生长过程中和之后不希望的界面化合物的形成，并且界面陷阱的密度降低。

22. 发明申请

US20080061284A1 Nanowire MOSFET with doped epitaxial contacts for source and drain 有权
标题翻译：具有用于源极和漏极的掺杂外延触点的纳米线MOSFET
公开(公告)号：US20080061284A1
公开(公告)日：2008-03-13
申请号：US11519176
申请日：2006-09-11
申请人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
发明人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/458 , H01L29/7839 , H01L29/785 , H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要翻译：公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。讨论了顶盖门控和底部门控纳米线FET结构。源极和漏极制造可以使用选择性或非选择性外延。

23. 发明授权

US06350993B1 High speed composite p-channel Si/SiGe heterostructure for field effect devices 失效
标题翻译：用于场效应器件的高速复合p沟道Si / SiGe异质结构
公开(公告)号：US06350993B1
公开(公告)日：2002-02-26
申请号：US09267323
申请日：1999-03-12
申请人： Jack Oon Chu , Richard Hammond , Khalid EzzEldin Ismail , Steven John Koester , Patricia May Mooney , John A. Ott
发明人： Jack Oon Chu , Richard Hammond , Khalid EzzEldin Ismail , Steven John Koester , Patricia May Mooney , John A. Ott
IPC分类号： H01L2906
CPC分类号： H01L29/7782 , H01L29/1025 , H01L29/1054
摘要： A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
摘要翻译：一种用于形成p沟道场效应晶体管的方法和分层异质结构被描述为在半导体衬底上并入多个半导体层，第一外延Ge层的复合沟道结构和具有较高势垒的第二压缩应变SiGe层更深的约束量子阱并具有极高的空穴迁移率。本发明克服了仅具有单个压缩应变SiGe沟道层的p沟道器件的有限空穴迁移率的问题。

24. 发明申请

US20120256281A1 SEMICONDUCTOR DEVICES HAVING NANOCHANNELS CONFINED BY NANOMETER-SPACED ELECTRODES 失效
标题翻译：具有纳米电极限制的纳米管的半导体器件
公开(公告)号：US20120256281A1
公开(公告)日：2012-10-11
申请号：US13430906
申请日：2012-03-27
申请人： Stefan Harrer , Stanislav Polonsky , Mark B. Ketchen , John A. Ott
发明人： Stefan Harrer , Stanislav Polonsky , Mark B. Ketchen , John A. Ott
IPC分类号： H01L29/66 , H01L21/283 , B82Y99/00
CPC分类号： H01L21/82 , B82Y15/00 , B82Y40/00 , Y10S977/958
摘要： Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.
摘要翻译：具有由纳米间隔电极限制的集成纳米通道的半导体器件和用于制造器件的VLSI（非常大规模集成）平面制造方法。半导体器件包括体基板和形成在本体基板上的第一金属层，其中第一金属层包括第一电极。纳米通道形成在第一金属层的上方，并且在长度方向上与本体基板的平面平行地延伸。第二金属层形成在纳米通道上，其中第二金属层包括第二电极。至少部分地由第二电极的表面限定纳米通道的顶壁，并且纳米通道的底壁由第一电极的表面限定。

25. 发明授权

US08153494B2 Nanowire MOSFET with doped epitaxial contacts for source and drain 有权
标题翻译：具有用于源极和漏极的掺杂外延触点的纳米线MOSFET
公开(公告)号：US08153494B2
公开(公告)日：2012-04-10
申请号：US12541371
申请日：2009-08-14
申请人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
发明人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/458 , H01L29/7839 , H01L29/785 , H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要翻译：公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。讨论了顶盖门控和底部门控纳米线FET结构。源极和漏极制造可以使用选择性或非选择性外延。

26. 发明申请

US20110086473A1 HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME 有权
标题翻译：具有减少边界缺陷的混合方向半导体结构及其形成方法
公开(公告)号：US20110086473A1
公开(公告)日：2011-04-14
申请号：US12972771
申请日：2010-12-20
申请人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
发明人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/02694 , H01L21/02532 , H01L21/76264 , Y10S438/973
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.
摘要翻译：本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片（011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

27. 发明授权

US07785939B2 Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers 失效
标题翻译：具有通过层叠模板层的局部非晶化和重结晶形成的所选半导体晶体取向的平面基板
公开(公告)号：US07785939B2
公开(公告)日：2010-08-31
申请号：US11566579
申请日：2006-12-04
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L21/02667 , H01L21/02609 , H01L21/2022 , H01L21/76251 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.
摘要翻译：提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

28. 发明申请

US20080108184A1 PLANAR SUBSTRATE WITH SELECTED SEMICONDUCTOR CRYSTAL ORIENTATIONS FORMED BY LOCALIZED AMORPHIZATION AND RECRYSTALLIZATION OF STACKED TEMPLATE LAYERS 失效
标题翻译：具有选择的半导体晶体取向的平面基板通过本地化的分解形成和堆叠的模板层的再结晶
公开(公告)号：US20080108184A1
公开(公告)日：2008-05-08
申请号：US11566579
申请日：2006-12-04
申请人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Katherine L. Saenger
发明人： Joel P. de Souza , John A. Ott , Alexander Reznicek , Katherine L. Saenger
IPC分类号： H01L21/84
CPC分类号： H01L21/02667 , H01L21/02609 , H01L21/2022 , H01L21/76251 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/1054 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.
摘要翻译：提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

29. 发明授权

US07084431B2 High speed composite p-channel Si/SiGe heterostructure for field effect devices 有权
标题翻译：用于场效应器件的高速复合p沟道Si / SiGe异质结构
公开(公告)号：US07084431B2
公开(公告)日：2006-08-01
申请号：US10832217
申请日：2004-04-26
申请人： Jack Oon Chu , Richard Hammond , Khalid EzzEldin Ismail , Steven John Koester , Patricia May Mooney , John A. Ott
发明人： Jack Oon Chu , Richard Hammond , Khalid EzzEldin Ismail , Steven John Koester , Patricia May Mooney , John A. Ott
IPC分类号： H01L27/15 , H01L29/06
CPC分类号： H01L29/7782 , H01L29/1025 , H01L29/1054
摘要： A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1−yGey, within a relaxed Si1−xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.
摘要翻译：提供了用于在其上形成电子器件的分层结构。层状结构包括在弛豫的Si 1-x Ge x x中的超射层，Si 1-y Y y Y y 其中y = X + Z，Z在0.01至0.1的范围内，X为0.35至0.5。超拍层具有小于其临界厚度的厚度。

30. 发明授权

US09472450B2 Graphene cap for copper interconnect structures 有权
标题翻译：用于铜互连结构的石墨烯盖
公开(公告)号：US09472450B2
公开(公告)日：2016-10-18
申请号：US13468693
申请日：2012-05-10
申请人： Griselda Bonilla , Christos D. Dimitrakopoulos , Alfred Grill , James B. Hannon , Qinghuang Lin , Deborah A. Neumayer , Satoshi Oida , John A. Ott , Dirk Pfeiffer
发明人： Griselda Bonilla , Christos D. Dimitrakopoulos , Alfred Grill , James B. Hannon , Qinghuang Lin , Deborah A. Neumayer , Satoshi Oida , John A. Ott , Dirk Pfeiffer
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76835 , H01L21/76846 , H01L21/76849 , H01L21/76852 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.
摘要翻译：提供了包括位于铜结构的暴露表面上的石墨烯盖的互连结构。在一些实施例中，石墨烯盖仅位于铜结构的最上表面的顶部，而在其它实施例中，石墨烯盖位于垂直侧壁和铜结构的最上表面的顶部。铜结构位于电介质材料内。

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