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1. 发明申请

US20120256281A1 SEMICONDUCTOR DEVICES HAVING NANOCHANNELS CONFINED BY NANOMETER-SPACED ELECTRODES 失效
标题翻译：具有纳米电极限制的纳米管的半导体器件
公开(公告)号：US20120256281A1
公开(公告)日：2012-10-11
申请号：US13430906
申请日：2012-03-27
申请人： Stefan Harrer , Stanislav Polonsky , Mark B. Ketchen , John A. Ott
发明人： Stefan Harrer , Stanislav Polonsky , Mark B. Ketchen , John A. Ott
IPC分类号： H01L29/66 , H01L21/283 , B82Y99/00
CPC分类号： H01L21/82 , B82Y15/00 , B82Y40/00 , Y10S977/958
摘要： Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.
摘要翻译：具有由纳米间隔电极限制的集成纳米通道的半导体器件和用于制造器件的VLSI（非常大规模集成）平面制造方法。半导体器件包括体基板和形成在本体基板上的第一金属层，其中第一金属层包括第一电极。纳米通道形成在第一金属层的上方，并且在长度方向上与本体基板的平面平行地延伸。第二金属层形成在纳米通道上，其中第二金属层包括第二电极。至少部分地由第二电极的表面限定纳米通道的顶壁，并且纳米通道的底壁由第一电极的表面限定。

2. 发明授权

US08558326B2 Semiconductor devices having nanochannels confined by nanometer-spaced electrodes 失效
标题翻译：具有由纳米间隔电极限制的纳米通道的半导体器件
公开(公告)号：US08558326B2
公开(公告)日：2013-10-15
申请号：US13430906
申请日：2012-03-27
申请人： Stefan Harrer , Stanislav Polonsky , Mark B. Ketchen , John A. Ott
发明人： Stefan Harrer , Stanislav Polonsky , Mark B. Ketchen , John A. Ott
IPC分类号： H01L27/14
CPC分类号： H01L21/82 , B82Y15/00 , B82Y40/00 , Y10S977/958
摘要： Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.
摘要翻译：具有由纳米间隔电极限制的集成纳米通道的半导体器件和用于制造器件的VLSI（非常大规模集成）平面制造方法。半导体器件包括体基板和形成在本体基板上的第一金属层，其中第一金属层包括第一电极。纳米通道形成在第一金属层的上方，并且在长度方向上与本体基板的平面平行地延伸。第二金属层形成在纳米通道上，其中第二金属层包括第二电极。至少部分地由第二电极的表面限定纳米通道的顶壁，并且纳米通道的底壁由第一电极的表面限定。

3. 发明申请

US20230046568A1 CIRCUITS FOR CONVERTING SFQ-BASED RZ AND NRZ SIGNALING TO BILEVEL VOLTAGE NRZ SIGNALING 有权
公开(公告)号：US20230046568A1
公开(公告)日：2023-02-16
申请号：US17401526
申请日：2021-08-13
申请人： Derek L. Knee , Mark B. Ketchen , Randall M. Burnett
发明人： Derek L. Knee , Mark B. Ketchen , Randall M. Burnett
IPC分类号： H03M5/14 , H03K19/003
摘要： Edge-sensitive, state-based single flux quantum (SFQ) based circuitry and related methods convert return-to-zero (RZ) or non-return-to-zero (NRZ) encoded SFQ-pulse-based signals to bilevel NRZ phase signals that can subsequently be converted to bilevel voltage signals by an output amplifier (OA). The SFQ-based circuitry can be integrated with a current amplification stage of a driver that can be coupled to a stage of the OA. The SFQ-based circuitry can be made to be compatible with RQL-encoded input signals that can be either RZ or NRZ. The SFQ-based circuitry can thus be compatible with both wave-pipelined (WPL) and phase-mode (PML) RQL circuitry. Because the SFQ-based circuitry and related methods are edge-sensitive and state-based, they can function at system clock rates in excess of 1 GHz with reduced glitches and improved bit error rates as compared to other superconducting RZ-NRZ conversion circuitry and methods.

4. 发明授权

US08456169B2 High speed measurement of random variation/yield in integrated circuit device testing 失效
标题翻译：集成电路设备测试中随机变化/产量的高速测量
公开(公告)号：US08456169B2
公开(公告)日：2013-06-04
申请号：US12686476
申请日：2010-01-13
申请人： Manjul Bhushan , Mark B. Ketchen , Qingqing Liang , Edward P. Maciejewski
发明人： Manjul Bhushan , Mark B. Ketchen , Qingqing Liang , Edward P. Maciejewski
IPC分类号： G01R31/02
CPC分类号： G01R31/2856 , G01R31/2894
摘要： A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.
摘要翻译：提供了一种测试结构，其利用时分采样技术以及使用金属氧化物半导体场效应晶体管（MOSFET）饱和度和线性特性的统计建模技术来测量平均值（平均）和σ（变化的统计特征））高速电气设备（如集成电路）的大量电气特性。这种电气特性或采样参数包括驱动电流，泄漏，电阻等

5. 发明申请

US20120166898A1 SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS 审中-公开
标题翻译：金属测试结构的单一级别，用于差分时序和集成电路的可变性测量
公开(公告)号：US20120166898A1
公开(公告)日：2012-06-28
申请号：US13410865
申请日：2012-03-02
申请人： Manjul Bhushan , Mark B. Ketchen , Chin Kim
发明人： Manjul Bhushan , Mark B. Ketchen , Chin Kim
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (Ml) in the integrated circuit device.
摘要翻译：用于集成电路装置的测试结构包括一个或多个实验，其被选择性地配置为接收一个或多个高速输入信号作为其输入并从其输出至少一个高速输出信号，所述一个或多个实验各自包括两个或多个逻辑门被配置为确定各个电路装置的差分延迟特性，其精度水平以皮秒级小于1皮秒; 并且其中所述一组或多组实验在所述集成电路器件中的金属布线（M1）的第一级处被布置并且是完全可测试的。

6. 发明申请

US20120161807A1 SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS 审中-公开
标题翻译：金属测试结构的单一级别，用于差分时序和集成电路的可变性测量
公开(公告)号：US20120161807A1
公开(公告)日：2012-06-28
申请号：US13410851
申请日：2012-03-02
申请人： Manjul Bhushan , Mark B. Ketchen , Chin Kim
发明人： Manjul Bhushan , Mark B. Ketchen , Chin Kim
IPC分类号： G01R31/26
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.
摘要翻译：用于集成电路装置的测试结构包括一个或多个实验，其被选择性地配置为接收一个或多个高速输入信号作为其输入并从其输出至少一个高速输出信号，所述一个或多个实验各自包括两个或多个逻辑门被配置为确定各个电路装置的差分延迟特性，其精度水平以皮秒级小于1皮秒; 并且其中所述一组或多组实验在所述集成电路装置中的金属布线（M1）的第一级处被布置并且是完全可测试的。

7. 发明授权

US08027797B2 Methods and apparatus for determining a switching history time constant in an integrated circuit device 有权
标题翻译：用于确定集成电路器件中的开关历史时间常数的方法和装置
公开(公告)号：US08027797B2
公开(公告)日：2011-09-27
申请号：US12110639
申请日：2008-04-28
申请人： Manjul Bhushan , Mark B. Ketchen , Dale J. Pearson
发明人： Manjul Bhushan , Mark B. Ketchen , Dale J. Pearson
IPC分类号： G01R25/00
CPC分类号： G01R31/31707 , G01R31/3016 , G01R31/31708 , H03K5/04
摘要： Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.
摘要翻译：提供了用于集成电路装置中的切换历史时间常数的在线测量的技术。一系列脉冲被发射到延迟链的第一级中，该延迟链包括多个串联连接的延迟级，其长度大于该系列脉冲中的至少初始脉冲的衰减长度，使得至少初始一系列脉冲之一不出现在延迟链的第二阶段。确定在延迟链的第二阶段发射一系列脉冲中的初始脉冲之一和至少一个脉冲串的出现之间的时间量。切换历史时间常数被计算为至少部分地基于至少一个脉冲遍历的次数的数量，所确定的时间量以及该系列脉冲中的至少初始脉冲的衰减长度的函数集成电路装置的切换历史。

8. 发明授权

US07595654B2 Methods and apparatus for inline variability measurement of integrated circuit components 失效
标题翻译：集成电路元件在线可变性测量方法与装置
公开(公告)号：US07595654B2
公开(公告)日：2009-09-29
申请号：US12041388
申请日：2008-03-03
申请人： Manjul Bhushan , Karen M. G. V. Gettings , Wilfried E. Haensch , Brian L. Ji , Mark B. Ketchen
发明人： Manjul Bhushan , Karen M. G. V. Gettings , Wilfried E. Haensch , Brian L. Ji , Mark B. Ketchen
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.
摘要翻译：提供一种集成电路器件，其包括至少一个集成电路部件的第一阵列结构，该集成电路部件包括一组FET，该集成电路阵列在集成电路部件之间没有规定的内部连接，其中m大于2。集成电路装置还包括集成电路部件的至少一个第二阵列配置，其包括与第一阵列配置的名义上相同的集成电路组件的阵列，以及集成电路部件之间的指定的内部连接。基于第一阵列配置和第二阵列配置的测量的指定参数来确定集成电路组件的变化系数。

9. 发明申请

US20080068099A1 Methods and apparatus for inline measurement of switching delay history effects in PD-SOI technology 有权
标题翻译：用于在线测量PD-SOI技术中开关延迟历史效应的方法和装置
公开(公告)号：US20080068099A1
公开(公告)日：2008-03-20
申请号：US11516139
申请日：2006-09-06
申请人： Manjul Bhushan , Mark B. Ketchen
发明人： Manjul Bhushan , Mark B. Ketchen
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： Techniques for inline measurement of switching delay history effects in an integrated circuit device are provided. A pulse is launched down a delay chain. The pulse is substantially synchronized with a signal of a ring oscillator. The delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain. At least one difference in a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain is measured when the pulse reaches the far end of the delay chain. One or more switching histories in the integrated circuit device are determined in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse.
摘要翻译：提供了用于集成电路装置中的开关延迟历史效应的在线测量的技术。一个脉冲在延迟链上发射。脉冲基本上与环形振荡器的信号同步。延迟链和环形振荡器包括与环形振荡器上对应于延迟链的远端的限定点基本相同的门。当脉冲到达延迟链的远端时，测量由环形振荡器中的信号边缘穿过的门数和由延迟链中的脉冲的相应边缘穿过的多个门中的至少一个差异。根据由信号的边缘和脉冲的对应边缘穿过的门数的至少一个测量的差异来确定集成电路器件中的一个或多个切换历史。

10. 发明授权

US07069525B2 Method and apparatus for determining characteristics of MOS devices 有权
标题翻译：用于确定MOS器件特性的方法和装置
公开(公告)号：US07069525B2
公开(公告)日：2006-06-27
申请号：US10623249
申请日：2003-07-18
申请人： Manjul Bhushan , Mark B. Ketchen
发明人： Manjul Bhushan , Mark B. Ketchen
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A set of ring oscillators is formed within a predetermined distance of each other. Each ring oscillator includes a number of coupled stages. The stages for a first given ring oscillator include an inverter having one or more first MOS devices having a first gate length. The stages for a second given ring oscillator include one or more second MOS devices having a second designed gate length. The stages for a third given ring oscillator comprise one or more third MOS devices having a third designed gate length. The second and third designed gate lengths are different and one of the second and third designed gate lengths is approximately equal to the first designed gate length. Performance is measured by using one of more of the given ring oscillators. The set of ring oscillators is used to determine one or more additional characteristics of MOS devices in the ring oscillators.
摘要翻译：一组环形振荡器形成在彼此的预定距离内。每个环形振荡器包括多个耦合级。第一给定环形振荡器的级包括具有一个或多个具有第一栅极长度的第一MOS器件的反相器。第二给定环形振荡器的级包括具有第二设计栅极长度的一个或多个第二MOS器件。第三给定环形振荡器的级包括具有第三设计栅极长度的一个或多个第三MOS器件。第二和第三设计的栅极长度是不同的，并且第二和第三设计的栅极长度之一近似等于第一设计栅极长度。通过使用更多的给定环形振荡器中的一个来测量性能。该组环形振荡器用于确定环形振荡器中的MOS器件的一个或多个附加特性。

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